參數(shù)資料
型號(hào)： CBTL06DP212EE
廠商： NXP SEMICONDUCTORS
元件分類： 編、解碼器及復(fù)用、解復(fù)用
英文描述： High-performance DisplayPort Gen2 2 : 1 multiplexer
中文描述： MULTIPLEXER, PBGA48
封裝： 5 X 5 MM, 0.80 MM HEIGHT, LEAD FREE, PLASTIC, TFBGA-48
文件頁(yè)數(shù)： 18/18頁(yè)
文件大小： 147K
代理商： CBTL06DP212EE
CBTL06DP212
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 21 February 2011
9 of 18
NXP Semiconductors
CBTL06DP212
High-performance DisplayPort Gen2 2 : 1 multiplexer
11. Characteristics
11.1 General characteristics
11.2 DisplayPort channel characteristics
Table 9.
General characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
IDD
supply current
VDD = 3.3 V
-
23mA
Pcons
power consumption
VDD = 3.3 V
--10
mW
tstartup
start-up time
supply voltage valid to channel specified
operating characteristics
--10
μs
trcfg
reconfiguration time
GPU_SEL or DDC_AUX_SEL state change
to channel specified operating characteristics
--1
μs
Table 10.
DisplayPort channel characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VI
input voltage
0.3
-
+2.6
V
VIC
common-mode input voltage
0
-
2.0
V
VID
differential input voltage
peak-to-peak
-
+1.2
V
Ron
ON-state resistance
VDD =3.3 V; VI =2V; II =20mA
-
6.5
-
Ω
DDIL
differential insertion loss
channel is ON; f
≤ 100 MHz
-
0.5
-
dB
channel is ON; f = 3.0 GHz
-
2.5
-
dB
channel is OFF; f
≤ 3.0 GHz
-
30
-
dB
DDRL
differential return loss
f = 100 MHz
-
25
-
dB
f= 3.0GHz
-
8-
dB
DDNEXT differential near-end crosstalk
adjacent channels are ON
f = 100 MHz
-
65
-
dB
f= 3.0GHz
-
35
-
dB
B
bandwidth
3.0 dB intercept
-
5
-
GHz
tPD
propagation delay
from left-side port to right-side port
or vice versa
-80
-
ps
tsk(dif)
differential skew time
intra-pair
-
5
-
ps
tsk
skew time
inter-pair
-
80
ps
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