SIGIN Input PC1 VCO adj" />
參數(shù)資料
型號(hào): CD74HC4046AEE4
廠商: Texas Instruments
文件頁(yè)數(shù): 13/34頁(yè)
文件大小: 0K
描述: IC PLL W/VCO 16-DIP
標(biāo)準(zhǔn)包裝: 25
系列: 74HC
類型: 鎖相環(huán)路(PLL)
PLL:
輸入: CMOS
輸出: CMOS
電路數(shù): 1
比率 - 輸入:輸出: 1:4
差分 - 輸入:輸出: 無(wú)/無(wú)
頻率 - 最大: 38MHz
除法器/乘法器: 無(wú)/無(wú)
電源電壓: 2 V ~ 6 V
工作溫度: -55°C ~ 125°C
安裝類型: 通孔
封裝/外殼: 16-DIP(0.300",7.62mm)
供應(yīng)商設(shè)備封裝: 16-PDIP
包裝: 管件
20
PLL Conditions with
No Signal at the
SIGIN Input
PC1
VCO adjusts to fo with φDEMOUT = 90
o and V
VCOIN = 1/2 VCC (see Figure 2)
PC2
VCO adjusts to fMIN with φDEMOUT = -360
o and V
VCOIN = 0V (see Figure 4)
PC3
VCO adjusts to fMAX with φDEMOUT = 360
o and V
VCOIN = VCC (see Figure 6)
PLL Frequency
Capture Range
PC1, PC2 or PC3
Loop Filter Component Selection
PLL Locks on
Harmonics at Center
Frequency
PC1 or PC3
Yes
PC2
No
Noise Rejection at
Signal Input
PC1
High
PC2 or PC3
Low
AC Ripple Content
when PLL is Locked
PC1
fr = 2fi, large ripple content at φDEMOUT = 90
o
PC2
fr = fi, small ripple content at φDEMOUT = 0
o
PC3
fr = fSIGIN, large ripple content at φDEMOUT = 180
o
SUBJECT
PHASE
COMPARATOR
DESIGN CONSIDERATIONS
A small capture range (2fc) is obtained if τ > 2fc 1/π (2πfL/τ.)
1/2
FIGURE 46. SIMPLE LOOP FILTER FOR PLL WITHOUT OFFSET
(A)
τ = R3 x C2
(B) AMPLITUDE CHARACTERISTIC
(C) POLE-ZERO DIAGRAM
R3
C2
INPUT
OUTPUT
|F(j
ω)|
ω
-1/
τ
FIGURE 47. SIMPLE LOOP FILTER FOR PLL WITH OFFSET
(A)
τ1 = R3 x C2;
(B) AMPLITUDE CHARACTERISTIC
(C) POLE-ZERO DIAGRAM
|F(j
ω)|
ω
-1/
τ2
R3
C2
INPUT
OUTPUT
τ2 = R4 x C2;
τ3 = (R3 + R4) x C2
-1/
τ3
m
1/
τ3 1/τ2
R4
m =
R4
R3 + R4
CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A
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