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參數(shù)資料
| 型號： | CDB4361 |
| 廠商： | Cirrus Logic Inc |
| 文件頁數(shù)： | 4/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR CS4361 |
| 標準包裝： | 1 |
| 系列： | Popguard® |
| DAC 的數(shù)量： | 6 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 192k |
| 數(shù)據(jù)接口： | 串行 |
| DAC 型： | 電壓 |
| 工作溫度： | -40°C ~ 85°C |
| 已供物品： | 板，CD |
| 已用 IC / 零件： | CDB4361 |
| 相關產(chǎn)品： | CS4361-CZZR-ND - IC DAC STER 6CH 105DB 20-TSSOP 598-1057-5-ND - IC DAC STER 6CH 103DB 20TSSOP |
| 其它名稱： | 598-1153 |
12
CS4361
Confidential Draft
9/30/11
4. APPLICATIONS
The CS4361 accepts data at standard audio sample rates including 48, 44.1 and 32 kHz in SSM, 96, 88.2 and
64 kHz in DSM, and 192, 176.4 and 128 kHz in QSM. Audio data is input via the serial data input pin (SDIN). The
Left/Right Clock (LRCK) determines which channel is currently being input on SDIN, and the optional Serial Clock
(SCLK) clocks audio data into the input data buffer.
4.1
Master Clock
MCLK/LRCK must be an integer ratio as shown in Table 1. The LRCK frequency is equal to Fs, the frequen-
cy at which words for each channel are input to the device. The MCLK-to-LRCK frequency ratio and speed
mode is detected automatically during the initialization sequence by counting the number of MCLK transi-
tions during a single LRCK period and by detecting the absolute speed of MCLK. Internal dividers are set
to generate the proper clocks. Table 1 illustrates several standard audio sample rates and the required
MCLK and LRCK frequencies. Please note there is no required phase relationship, but MCLK, LRCK, and
SCLK must be synchronous.
Table 1. Common Clock Frequencies
4.2
Serial Clock
The serial clock controls the shifting of data into the input data buffers. The CS4361 supports both external
and internal serial clock generation modes. Refer to Figures 7-10 for data formats.
4.2.1
External Serial Clock Mode
The CS4361 will enter the External Serial Clock Mode when 16 low-to-high transitions are detected on
the DEM/SCLK pin during any phase of the LRCK period. When this mode is enabled, the Internal Serial
Clock Mode and de-emphasis filter cannot be accessed. The CS4361 will switch to Internal Serial Clock
Mode if no low-to-high transitions are detected on the DEM/SCLK pin for two consecutive frames of
LRCK. Refer to Figure 12.
4.2.2
Internal Serial Clock Mode
In the Internal Serial Clock Mode, the serial clock is internally derived and synchronous with MCLK and
LRCK. The SCLK/LRCK frequency ratio is either 32, 48, 64, or 72 depending upon data format. Operation
in this mode is identical to operation with an external serial clock synchronized with LRCK. This mode al-
LRCK
(kHz)
MCLK (MHz)
64x
96x
128x
192x
256x
384x
512x
768x
1024x
1152x
32
-
---
8.1920
12.2880
-
32.7680
36.8640
44.1
-
---
11.2896
16.9344
22.5792
33.8680
45.1580
-
48
-
---
12.2880
18.4320
24.5760
36.8640
49.1520
-
64
-
8.1920
12.2880
-
32.7680
49.1520
-
88.2
-
11.2896
16.9344
22.5792
33.8680
-
96
-
12.2880
18.4320
24.5760
36.8640
-
128
8.1920
12.2880
-
32.7680
49.1520
-
176.4
11.2896
16.9344
22.5792
33.8680
-
192
12.2880
18.4320
24.5760
36.8640
-
Mode
QSM
DSM
SSM
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