- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄17060 > CDB4361 (Cirrus Logic Inc)BOARD EVAL FOR CS4361 PDF資料下載
參數(shù)資料
| 型號(hào)： | CDB4361 |
| 廠商： | Cirrus Logic Inc |
| 文件頁數(shù)： | 6/24頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR CS4361 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | Popguard® |
| DAC 的數(shù)量： | 6 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 192k |
| 數(shù)據(jù)接口： | 串行 |
| DAC 型： | 電壓 |
| 工作溫度： | -40°C ~ 85°C |
| 已供物品： | 板，CD |
| 已用 IC / 零件： | CDB4361 |
| 相關(guān)產(chǎn)品： | CS4361-CZZR-ND - IC DAC STER 6CH 105DB 20-TSSOP 598-1057-5-ND - IC DAC STER 6CH 103DB 20TSSOP |
| 其它名稱： | 598-1153 |
14
CS4361
Confidential Draft
9/30/11
4.3
De-Emphasis
The CS4361 includes on-chip digital de-emphasis. Figure 11 shows the de-emphasis curve for Fs equal to
44.1 kHz. The frequency response of the de-emphasis curve will scale proportionally with changes in sam-
ple rate, Fs. The de-emphasis filter is active (inactive) if the DEM/SCLK pin is low (high) for five consecutive
falling edges of LRCK. This function is available only in the internal Serial Clock Mode when LRCK < 50 kHz.
4.4
Mode Select
Mode selection is determined by the Mode Select pin. The value of this pin is locked 1024 LRCK cycles after
RST is released. This pin requires a specific connection to supply, ground, MCLK, or LRCK as outlined in
Table 2. Mode Pin Settings
Mode pin is:
Mode
Figure
Tied to VL
IS
Tied to GND
Left-Justified
Tied to LRCK
Right-Justified - 24 bit
Tied to MCLK
Right-Justified - 16bit
LRCK
SCLK
Left Channel
Right Channel
SDATA
654321
0
98
7
15 14 13 12 11 10
6543
210
98
7
15 14 13 12 11 10
32 clocks
Internal SCLK Mode
External SCLK Mode
Right-Justified, 16-Bit Data
INT SCLK = 32 Fs if
MCLK/LRCK = 1024, 512, 256, 128, or 64
INT SCLK = 48 Fs if
MCLK/LRCK = 768, 384, 192, or 96
INT SCLK = 72 Fs if
MCLK/LRCK = 1152
Right-Justified, 16-Bit Data
Data Valid on Rising Edge of SCLK
SCLK Must Have at Least 32 Cycles per LRCK Period
Figure 10. CS4361 Data Format (Right-Justified 16)
Gain
dB
-10dB
0dB
Frequency
T2 = 15 s
T1=50 s
F1
F2
3.183 kHz
10.61 kHz
Figure 11. De-Emphasis Curve (Fs = 44.1kHz)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| RCM15DCCH-S189 | CONN EDGECARD 30POS R/A .156 SLD |
| CDB4334 | BOARD EVAL FOR CS4334 CODEC |
| VE-B3R-EY | CONVERTER MOD DC/DC 7.5V 50W |
| 0210391031 | CABLE JUMPER 1MM .030M 33POS |
| EVAL-AD7356EDZ | BOARD EVAL AD7356 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CDB4362 | 制造商:Cirrus Logic 功能描述:Tools Development kit Kit Con |
| CDB4362A | 功能描述:音頻 IC 開發(fā)工具 Eval Bd 1142dB 24Bit 192kHz DAC RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Kits 類型:Audio Amplifiers 工具用于評(píng)估:TAS5614L 工作電源電壓:12 V to 38 V |
| CDB4364 | 功能描述:音頻 IC 開發(fā)工具 Eval Bd 6-Ch DAC w/DSD RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Kits 類型:Audio Amplifiers 工具用于評(píng)估:TAS5614L 工作電源電壓:12 V to 38 V |
| CDB4365 | 功能描述:音頻 IC 開發(fā)工具 Eval Bd 6-Ch DAC w/DSD RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Kits 類型:Audio Amplifiers 工具用于評(píng)估:TAS5614L 工作電源電壓:12 V to 38 V |
| CDB4382 | 制造商:Cirrus Logic 功能描述:Tools Development kit Kit Con |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。