參數(shù)資料
型號: CDB4361
廠商: Cirrus Logic Inc
文件頁數(shù): 5/24頁
文件大?。?/td> 0K
描述: BOARD EVAL FOR CS4361
標準包裝: 1
系列: Popguard®
DAC 的數(shù)量: 6
位數(shù): 24
采樣率(每秒): 192k
數(shù)據(jù)接口: 串行
DAC 型: 電壓
工作溫度: -40°C ~ 85°C
已供物品: 板,CD
已用 IC / 零件: CDB4361
相關產(chǎn)品: CS4361-CZZR-ND - IC DAC STER 6CH 105DB 20-TSSOP
598-1057-5-ND - IC DAC STER 6CH 103DB 20TSSOP
其它名稱: 598-1153
13
CS4361
Confidential Draft
9/30/11
LRCK
SCLK
Left Channel
Right Channel
SDATA
+3 +2 +1 LSB
+5 +4
MSB -1 -2 -3 -4 -5
+3 +2 +1 LSB
+5 +4
MSB -1 -2 -3 -4
Internal SCLK Mode
External SCLK Mode
IS, 16-Bit data and INT SCLK = 32 Fs if
MCLK/LRCK = 1024, 512, 256, 128, or 64
IS, Up to 24-Bit data and INT SCLK = 48 Fs if
MCLK/LRCK = 768, 384, 192, or 96
IS, Up to 24-Bit data and INT SCLK = 72 Fs if
MCLK/LRCK = 1152
IS, up to 24-Bit Data
Data Valid on Rising Edge of SCLK
Figure 7. CS4361 Data Format (IS)
LRCK
SCLK
Left Channel
Right Channel
SDATA
+3 +2 +1 LSB
+5 +4
MSB -1 -2 -3 -4 -5
+3 +2 +1 LSB
+5 +4
MSB -1 -2 -3 -4
Internal SCLK Mode
External SCLK Mode
Left-Justified, up to 24-Bit Data
INT SCLK = 64 Fs if
MCLK/LRCK = 1024, 512, 256, 128, or 64
INT SCLK = 48 Fs if
MCLK/LRCK = 768, 384, 192, or 96
INT SCLK = 72 Fs if
MCLK/LRCK = 1152
Left-Justified, up to 24-Bit Data
Data Valid on Rising Edge of SCLK
Figure 8. CS4361 Data Format (Left-Justified)
LRCK
SCLK
Left Channel
SDATA
65
4321
0
7
23 22 21 20 19 18
6543
210
7
23 22 21 20 19 18
32 clocks
0
Right Channel
Internal SCLK Mode
External SCLK Mode
Right-Justified, 24-Bit Data
INT SCLK = 64 Fs if
MCLK/LRCK = 1024, 512, 256, 128, or 64
INT SCLK = 48 Fs if
MCLK/LRCK = 768, 384, 192, or 96
INT SCLK = 72 Fs if
MCLK/LRCK = 1152
Right-Justified, 24-Bit Data
Data Valid on Rising Edge of SCLK
SCLK Must Have at Least 48 Cycles per LRCK Period
Figure 9. CS4361 Data Format (Right-Justified 24)
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