參數(shù)資料
型號(hào)： CLRC63201T
廠商： NXP Semiconductors N.V.
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Multiple protocol contactless reader IC (MIFARE-I-CODE1)
封裝： CLRC63201T/0FE<SOT287-1 (SO32)|<<http://www.nxp.com/packages/SOT287-1.html<1<week 5, 2005,;
文件頁數(shù)： 41/126頁
文件大小： 719K
代理商： CLRC63201T
CLRC632_35
NXP B.V. 2009. All rights reserved.
Product data sheet
PUBLIC
Rev. 3.5 — 10 November 2009
073935
21 of 126
NXP Semiconductors
CLRC632
Multiple protocol contactless reader IC (MIFARE/I-CODE1)
9.4.1 Interrupt sources overview
Table 20 shows the integrated interrupt ags, related source and setting condition. The
interrupt TimerIRq ag bit indicates an interrupt set by the timer unit. Bit TimerIRq is set
when the timer decrements from one down to zero (bit TAutoRestart disabled) or from one
to the TReLoadValue[7:0] with bit TAutoRestart enabled.
Bit TxIRq indicates interrupts from different sources and is set as follows:
the transmitter automatically sets the bit TxIRq interrupt when it is active and its state
changes from sending data to transmitting the end of frame pattern
the CRC coprocessor sets the bit TxIRq after all data from the FIFO buffer has been
processed indicated by bit CRCReady = logic 1
when EEPROM programming is nished, the bit TxIRq is set and is indicated by bit
E2Ready = logic 1
The RxIRq ag bit indicates an interrupt when the end of the received data is detected.
The IdleIRq ag bit is set when a command nishes and the content of the Command
register changes to Idle.
When the FIFO buffer reaches the HIGH-level indicated by the WaterLevel[5:0] value (see
Section 9.3.3 on page 20) and bit HiAlert = logic 1, then the HiAlertIRq ag bit is set to
logic 1.
When the FIFO buffer reaches the LOW-level indicated by the WaterLevel[5:0] value (see
Section 9.3.3 on page 20) and bit LoAlert = logic 1, then LoAlertIRq ag bit is set to
logic 1.
9.4.2 Interrupt request handling
9.4.2.1
Controlling interrupts and getting their status
The CLRC632 informs the microprocessor about the interrupt request source by setting
the relevant bit in the InterruptRq register. The relevance of each interrupt request bit as
source for an interrupt can be masked by the InterruptEn register interrupt enable bits.
Table 20.
Interrupt sources
Interrupt ag
Interrupt source
Trigger action
TimerIRq
timer unit
timer counts from 1 to 0
TxIRq
transmitter
a data stream, transmitted to the card, ends
CRC coprocessor
all data from the FIFO buffer has been processed
EEPROM
all data from the FIFO buffer has been
programmed
RxIRq
receiver
a data stream, received from the card, ends
IdleIRq
Command register
command execution nishes
HiAlertIRq
FIFO buffer
FIFO buffer is full
LoAlertIRq
FIFO buffer
FIFO buffer is empty
Table 21.
Interrupt control registers
Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
InterruptEn
SetIEn
reserved
TimerIEn
TxIEn
RxIEn
IdleIEn
HiAlertIEn
LoAlertIEn
InterruptRq
SetIRq
reserved
TimerIRq
TxIRq
RxIRq
IdleIRq
HiAlertIRq
LoAlertIRq
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參數(shù)描述
CLRC63201T/0FE 制造商:NXP Semiconductors 功能描述:
CLRC63201T/0FE,112 功能描述:RFID應(yīng)答器 I.CODE HS READER RoHS:否 制造商:Murata 存儲(chǔ)容量:512 bit 工作溫度范圍:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel
CLRC63201T/0FE,118 制造商:NXP Semiconductors 功能描述:Interface Misc
CLRC63201T/0FE112 制造商:NXP Semiconductors 功能描述:CNTCLESS RC 5V ISO14443 + ISO15693
CLRC663 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Contactless reader IC
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