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CLRC632_35
NXP B.V. 2009. All rights reserved.
Product data sheet
PUBLIC
Rev. 3.5 — 10 November 2009
073935
53 of 126
NXP Semiconductors
CLRC632
Multiple protocol contactless reader IC (MIFARE/I-CODE1)
10.5.1.6
SecondaryStatus register
Various secondary status ags.
10.5.1.7
InterruptEn register
Control bits to enable and disable passing of interrupt requests.
[1]
This bit can only be set or cleared using bit SetIEn.
Table 51.
SecondaryStatus register (address: 05h) reset value: 01100 000b, 60h bit
allocation
Bit
7
6
5
4
3
2
1
0
Symbol
TRunning
E2Ready
CRCReady
00
RxLastBits[2:0]
Access
R
Table 52.
SecondaryStatus register bit descriptions
Bit
Symbol
Value
Description
7
TRunning
1
the timer unit is running and the counter decrements the
TimerValue register on the next timer clock cycle
0
the timer unit is not running
6
E2Ready
1
EEPROM programming is nished
0
EEPROM programming is ongoing
5
CRCReady
1
CRC calculation is nished
0
CRC calculation is ongoing
4 to 3
00
-
reserved
2 to 0
RxLastBits
[2:0]
-
shows the number of valid bits in the last received byte. If zero, the
whole byte is valid
Table 53.
InterruptEn register (address: 06h) reset value: 0000 0000b, 00h bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
SetIEn
0
TimerIEn
TxIEn
RxIEn
IdleIEn
HiAlertIEn
LoAlertIEn
Access
W
R/W
Table 54.
InterruptEn register bit descriptions
Bit
Symbol
Value
Description
7
SetIEn
1
indicates that the marked bits in the InterruptEn register are set
0
clears the marked bits
6
0
-
reserved
5
TimerIEn
-
sends the TimerIRq timer interrupt request to pin
IRQ[1]4
TxIEn
-
sends the TxIRq transmitter interrupt request to pin IRQ
[1]3
RxIEn
-
sends the RxIRq receiver interrupt request to pin
IRQ[1]2
IdleIEn
-
sends the IdleIRq idle interrupt request to pin IRQ
[1]1
HiAlertIEn
-
sends the HiAlertIRq high alert interrupt request to pin
IRQ[1]0
LoAlertIEn -
sends the LoAlertIRq low alert interrupt request to pin IRQ
[1]