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參數資料
| 型號： | CP2104-F03-GM |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數： | 5/22頁 |
| 文件大小： | 0K |
| 描述： | IC SGL USB-TO-UART BRIDGE 24QFN |
| 產品培訓模塊： | CP21xx USB Bridge |
| 標準包裝： | 75 |
| 應用： | UART 至 USB 電橋 |
| 接口： | UART，USB |
| 電源電壓： | 1.8V，3 V ~ 3.6 V |
| 封裝/外殼： | 24-WFQFN 裸露焊盤 |
| 供應商設備封裝： | 24-QFN（4x4） |
| 包裝： | 管件 |
| 安裝類型： | 表面貼裝 |
| 配用： | 336-2007-ND - KIT EVAL FOR CP2104 |
| 其它名稱： | 336-2008-5 |
CP2104
Rev. 1.1
13
6.1. Baud Rate Generation
The baud rate generator is very flexible, allowing the user to request any baud rate in the range from 300 bps to
2 Mbps. If the baud rate cannot be directly generated from the 48 MHz oscillator, the device will choose the closest
possible option. The actual baud rate is dictated by Equation 1 and Equation 2.
Equation 1. Clock Divider Calculation
Equation 2. Baud Rate Calculation
Most baud rates can be generated with an error of less than 1.0%. A general rule of thumb for the majority of UART
applications is to limit the baud rate error on both the transmitter and the receiver to no more than ±2%. The clock
divider value obtained in Equation 1 is rounded to the nearest integer, which may produce an error source. Another
error source will be the 48 MHz oscillator, which is accurate to ±0.25%. Knowing the actual and requested baud
rates, the total baud rate error can be found using Equation 3.
Equation 3. Baud Rate Error Calculation
7. GPIO Pins
The CP2104 supports four user-configurable GPIO pins for status and control information. Each of these GPIO
pins are usable as inputs, open-drain outputs, or push-pull outputs. Three of these GPIO pins also have alternate
functions which are listed in Table 11.
By default, all of the GPIO pins are configured as a GPIO input. The configuration of the pins is one-time
programmable for each device. The difference between an open-drain output and a push-pull output is when the
GPIO output is driven to logic high. A logic high, open-drain output pulls the pin to the VIO rail through an internal,
pull-up resistor. A logic high, push-pull output directly connects the pin to the VIO voltage. Open-drain outputs are
typically used when interfacing to logic at a higher voltage than the VIO pin. These pins can be safely pulled to the
higher, external voltage through an external pull-up resistor. The maximum external pull-up voltage is 5 V.
The speed of reading and writing the GPIO pins is subject to the timing of the USB bus. GPIO pins configured as
inputs or outputs are not recommended for real-time signaling.
More information regarding the configuration and usage of these pins can be found in “AN721: CP21xx Device
Customization Guide” and “AN223: Runtime GPIO Control for CP210x” available on the Silicon Labs website.
Table 11. GPIO Pin Alternate Functions
GPIO Pin
Alternate Function
GPIO.0
TX Toggle
GPIO.1
RX Toggle
GPIO.2
RS-485 Transceiver Control
Clock Divider
48 MHz
2
Prescale
Requested Baud Rate
----------------------------------------------------------------------------------------------------
=
Prescale
4 if Requested Baud Rate
365 bps
=
Prescale
1 if Requested Baud Rate
365 bps
=
Actual Baud Rate
48 MHz
2
Prescale
Clock Divider
-----------------------------------------------------------------------------
=
Prescale
4 if Requested Baud Rate
365 bps
=
Prescale
1 if Requested Baud Rate
365 bps
=
Baud Rate Error (%)
100
1
Actual Baud Rate
Requested Baud Rate
-----------------------------------------------------------
–
0.25%
=
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相關代理商/技術參數 |
參數描述 |
|---|---|
| CP2104-F03-GMR | 功能描述:輸入/輸出控制器接口集成電路 USB to UART bridge RoHS:否 制造商:Silicon Labs 產品: 輸入/輸出端數量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray |
| CP2104-MINIEK | 制造商:Silicon Laboratories Inc 功能描述:KIT EVAL FOR CP2104-MINI |
| CP2104SX0810GM | 制造商:Silicon Laboratories Inc 功能描述: |
| CP2104SX0810GMR | 制造商:Silicon Laboratories Inc 功能描述: |
| CP2105 | 制造商:SILABS 制造商全稱:SILABS 功能描述:USB DRIVER CUSTOMIZATION |
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