參數(shù)資料
型號： CP2201-GM
廠商： Silicon Laboratories Inc
文件頁數(shù)： 73/108頁
文件大小： 0K
描述： IC ETH CTRLR SNGL-CHIP 28QFN
標(biāo)準(zhǔn)包裝： 73
控制器類型： 以太網(wǎng)控制器，MAC/10Base-T
接口： 并行/串行
電源電壓： 3.1 V ~ 3.6 V
電流 - 電源： 75mA
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 28-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 28-QFN（5x5）
包裝： 管件
產(chǎn)品目錄頁面： 627 (CN2011-ZH PDF)
配用： 336-1326-ND - KIT REF DESIGN PWR OVER ETHERNET
336-1316-ND - KIT EVAL FOR CP2201 ETH CTRLR
其它名稱： 336-1313
CP2200/1
Rev. 1.0
67
The Receive FIFO Full interrupt will be generated once all free space in the buffer is used or all TLB slots are filled.
The host processor should read the RXFIFOSTA register to determine the cause of the interrupt. To receive
additional packets after the buffer is filled, packets must be removed from the buffer by reading them out or
discarding them. Packets can be discarded one at a time or all at once by writing ‘1’ to RXCLEAR (RXCN.0).
12.7. Receive Buffer Advanced Status and Control Registers
The receive buffer is controlled and managed through the registers in Table 17. These registers are not commonly
accessed by the host processor except for debug purposes.
Register 46. CPTLB: Current Packet TLB Number
Table 17. Receive Status and Control Register Summary
Register
Long Name
Address
Description
CPTLB
Current Packet TLB Number
0x1A
Specifies the TLB number (0–7) associated with
the current packet.
TLBVALID
TLB Valid Indicator
0x1C
Indicates which TLBs currently have valid pack-
ets.
TLBnINFOH
TLBnINFOL
TLBn Packet Information
multiple
Specifies information about the packet associ-
ated with TLBn (n = 0–7).
TLBLENH
TLBLENL
TLBn Packet Length
multiple
Specifies the length of the packet associated
with TLBn (n = 0–7).
TLBnADDRH
TLBnADDRL
TLBn Packet Address
multiple
Specifies the starting address of the packet
associated with TLBn (n = 0–7).
RXFIFOTAILH
RXFIFOTAILL
Receive FIFO Buffer Tail Pointer
0x15
0x16
Points to the byte following the last valid byte.
This is where new packets are added.
RXFIFOHEADH
RXFIFOHEADL
Receive FIFO Buffer Head
Pointer
0x17
0x18
Points to the beginning of the current packet
and is incremented with each Auto Read.
RXFIFOSTA
Receive FIFO Buffer Status
0x5B
Indicates the cause of the Receive FIFO Buffer
Full interrupt.
Bits 7–3: UNUSED. Read = 00000b; Write = don’t care.
Bits 2–0: CPTLB[2:0]: Current Packet TLB Number
The TLB Number (0–7) of the TLB slot associated with the current packet.
R/W
Reset Value
—
CPTLB
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Address:
0x1A
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