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參數(shù)資料
| 型號： | CP82C89 |
| 廠商： | Intersil |
| 文件頁數(shù)： | 8/13頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ARBITER BUS 5V 8MHZ 20-DIP |
| 標準包裝： | 180 |
| 控制器類型： | CMOS 優(yōu)先中斷控制器 |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 電流 - 電源： | 1mA |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 20-DIP（0.300"，7.62mm） |
| 供應(yīng)商設(shè)備封裝： | 20-PDIP |
| 包裝： | 管件 |
4
FN2980.2
February 27, 2006
Priority Resolving Techniques
Since there can be many bus masters on a multi-master
system bus, some means of resolving priority between bus
masters simultaneously requesting the bus must be
provided. The 82C89 Bus Arbiter provides several resolving
techniques. All the techniques are based on a priority
concept that at a given time one bus master will have priority
above all the rest. There are provisions for using parallel
priority resolving techniques, serial priority resolving
techniques, and rotating priority techniques.
Parallel Priority Resolving
The parallel priority resolving technique uses a separate bus
request line BREQ for each arbiter on the multi-master
system bus, see Figure 1. Each BREQ line enters into a
priority encoder which generates the binary address of the
highest priority BREQ line which is active. The binary address
is decoded by a decoder to select the corresponding BPRN
(Bus Priority In) line to be returned to the highest priority
requesting arbiter. The arbiter receiving priority (BPRN true)
then allows its associated bus master onto the multi-master
system bus as soon as it becomes available (i.e., the bus is
no longer busy). When one bus arbiter gains priority over
another arbiter it cannot immediately seize the bus, it must
wait until the present bus transaction is complete. Upon
completing its transaction the present bus occupant
recognizes that it no longer has priority and surrenders the
bus by releasing BUSY. BUSY is an active low “OR” tied
signal line which goes to every bus arbiter on the system
bus. When BUSY goes inactive (high), the arbiter which
presently has bus priority (BPRN true) then seizes the bus
and pulls BUSY low to keep other arbiters off of the bus. See
waveform timing diagram, Figure 2. Note that all multimaster
system bus transactions are synchronized to the bus clock
(BCLK). This allows the parallel priority resolving circuitry or
any other priority resolving scheme employed to settle.
NOTES:
1. Higher priority bus arbiter releases BUSY.
2. Higher priority bus arbiter then acquires the bus and pulls BUSY
down.
3. Lower priority bus arbiter releases BUSY.
4. Higher priority bus arbiter then acquires the bus and pulls BUSY
down.
Serial Priority Resolving
The serial priority resolving technique eliminates the need
for the priority encoder-decoder arrangement by
daisychaining the bus arbiters together, connecting the
higher priority bus arbiter’s BPRO (Bus Priority Out) output
to the BPRN of the next lower priority. See Figure 3.
Rotating Priority Resolving
The rotating priority resolving technique is similar to that of
the parallel priority resolving technique except that priority is
dynamically re-assigned. The priority encoder is replaced by
a more complex circuit which rotates priority between
requesting arbiters thus allowing each arbiter an equal
chance to use the multi-master system bus, over time.
BUS
ARBITER
1
BUS
ARBITER
2
BUS
ARBITER
3
BUS
ARBITER
4
74HC148
PRIORITY
ENCODER
74HC138
3 TO 8
ENCODER
BREQ
BPRN
BREQ
BPRN
BREQ
BPRN
BREQ
BPRN
BUS
Y
CBRQ
FIGURE 1. PARALLEL PRIORITY RESOLVING TECHNIQUE
BCLK
BREQ
BPRN
BUSY
1
2
3
4
FIGURE 2. HIGHER PRIORITY ARBITER OBTAINING THE
BUS FROM A LOWER PRIORITY ARBITER
BUS
ARBITER
1
BUS
ARBITER
2
BUS
ARBITER
3
BUS
ARBITER
4
BPRN
BUSY
CBRQ
BPRO
BPRN
FIGURE 3. SERIAL PRIORITY RESOLVING
NOTE: The number of arbiters that may be daisy-chained together
in the serial priority resolving scheme is a function of BCLK and the
propagation delay from arbiter to arbiter. Normally, at 10MHz only 3
arbiters may be daisychained.
82C89
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