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參數(shù)資料
| 型號(hào)： | CP82C89 |
| 廠商： | Intersil |
| 文件頁(yè)數(shù)： | 9/13頁(yè) |
| 文件大小： | 0K |
| 描述： | IC ARBITER BUS 5V 8MHZ 20-DIP |
| 標(biāo)準(zhǔn)包裝： | 180 |
| 控制器類(lèi)型： | CMOS 優(yōu)先中斷控制器 |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 電流 - 電源： | 1mA |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類(lèi)型： | 通孔 |
| 封裝/外殼： | 20-DIP（0.300"，7.62mm） |
| 供應(yīng)商設(shè)備封裝： | 20-PDIP |
| 包裝： | 管件 |
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5
FN2980.2
February 27, 2006
Which Priority Resolving Technique To Use
There are advantages and disadvantages for each of the
techniques described above. The rotating priority resolving
technique requires substantial external logic to implement
while the serial technique uses no external logic but can
accommodate only a limited number of bus arbiters before the
daisy-chain propagation delay exceeds the multimaster’s
system bus clock (BCLK). The parallel priority resolving
technique is in general a good compromise between the other
two techniques. It allows for many arbiters to be present on
the bus while not requiring too much logic to implement.
82C89 Modes Of Operation
There are two types of processors for which the 82C89 will
provide support: An Input/Output processor (i.e. an NMOS
8089 IOP) and the 80C86, 80C88. Consequently, there are
two basic operating modes in the 82C89 bus arbiter. One,
the IOB (I/O Peripheral Bus) mode, permits the processor
access to both an I/O Peripheral Bus and a multi-master
system bus. The second, the RESB (Resident Bus mode),
permits the processor to communicate over both a Resident
Bus and a multi-master system bus. An I/O Peripheral Bus is
a bus where all devices on that bus, including memory, are
treated as I/O devices and are addressed by I/O commands.
All memory commands are directed to another bus, the
multi-master system bus. A Resident Bus can issue both
memory and I/O commands, but it is a distinct and separate
bus from the multi-master system bus. The distinction is that
the Resident Bus has only one master, providing full
availability and being dedicated to that one master.
The IOB strapping option configures the 82C89 Bus Arbiter
into the IOB mode and the strapping option RESB
configures it into the RESB mode. It might be noted at this
point that if both strapping options are strapped false, the
arbiter interfaces the processor to a multi-master system bus
only (see Figure 4). With both options strapped true, the
arbiter interfaces the processor to a multi-master system
bus, a Resident Bus, and an I/O Bus.
In the IOB mode, the processor communicates and controls
a host of peripherals over the Peripheral Bus. When the I/O
Processor needs to communicate with system memory, it
does so over the system memory bus. Figure 5 shows a
possible I/O Processor system configuration.
The 80C86 and 80C88 processors can communicate with a
Resident Bus and a multi-master system bus. Two bus
controllers and only one Bus Arbiter would be needed in
such a configuration as shown in Figure 6. In such a system
configuration the processor would have access to memory
and peripherals of both busses. Memory mapping
techniques are applied to select which bus is to be
accessed. The SYSB/RESB input on the arbiter serves to
instruct the arbiter as to whether or not the system bus is to
be accessed. The signal connected to SYSB/RESB also
enables or disables commands from one of the bus
controllers. A summary of the modes that the 82C89 has,
along with its response to its status lines inputs, is shown in
Table 1.
82C89
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