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參數(shù)資料
| 型號(hào)： | CS42L52-DNZR |
| 廠商： | CIRRUS LOGIC INC |
| 元件分類： | 消費(fèi)家電 |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, QCC40 |
| 封裝： | 6 X 6 MM, LEAD FREE, MO-220, QFN-40 |
| 文件頁數(shù)： | 31/59頁 |
| 文件大?。?/td> | 1800K |
| 代理商： | CS42L52-DNZR |
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DS680F1
37
CS42L52
5/13/08
4.8
Initialization
The CODEC enters a Power-down state upon initial power-up. The interpolation and decimation filters, del-
ta-sigma and PWM modulators, and control port registers are reset. The internal voltage reference, and
switched-capacitor low-pass filters are powered down.
The device will remain in the Power-down state until the RESET pin is brought high. The control port is ac-
cessible once RESET is high and the desired register settings can be loaded per the interface descriptions
Once MCLK is valid, the quiescent voltage, VQ, and the internal voltage reference, FILT+, will begin power-
ing up to normal operation. The charge pump slowly powers up and charges the capacitors. Power is then
applied to the headphone amplifiers and switched-capacitor filters, and the analog/digital outputs enter a mut-
ed state. Once LRCK is valid, MCLK occurrences are counted over one LRCK period to determine the
MCLK/LRCK frequency ratio and normal operation begins.
4.9
Recommended Power-up Sequence
1.
Hold RESET low until the power supplies are stable.
2.
Bring RESET high.
3.
The default state of the PDN bit is ‘1’b. Load the desired register settings while keeping the PDN bit set
to ‘1’b.
4.
Load the required initialization settings listed in Section 4.11.
5.
Start MCLK to the appropriate frequency, as discussed in Section 4.6.
6.
Set the PDN bit to ‘0’b.
7.
Apply LRCK, SCLK, and SDIN for normal operation to begin.
8.
Bring RESET low if the analog or digital supplies drop below the recommended operating condition to
prevent power glitch related issues.
4.10
Recommended Power-down Sequence
To minimize audible pops when turning off or placing the CODEC in standby:
1.
Mute the DAC’s and ADC’s.
2.
Set the PDN bit in the power control register to ‘1’b. The CODEC will not power down until it reaches a
fully muted sate. Do not remove MCLK until after the part has fully muted. Note that it may be necessary
to disable the soft-ramp and/or zero-cross volume transitions to achieve faster muting/power down.
3.
Bring RESET low.
4.11
Required Initialization Settings
The current and thresholds required for various sections in the CODEC must be adjusted by implementing
the initialization settings shown below after power-up sequence step 3. All performance and power con-
sumption measurements were taken with the following settings:
1.
Write 0x99 to register 0x00.
2.
Write 0xBA to register 0x3E.
3.
Write 0x80 to register 0x47.
4.
Write ‘1’b to bit 7 in register 0x32.
5.
Write ‘0’b to bit 7 in register 0x32.
6.
Write 0x00 to register 0x00.
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| CS42L55 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:Ultra Low Power, Stereo CODEC w/Class H Headphone Amp |
| CS42L55-CNZ | 功能描述:接口—CODEC IC Ultra Low Power Stereo Codec RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| CS42L55-CNZR | 功能描述:接口—CODEC IC Ultra Low PWR Stereo Codec RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| CS42L55-DNZ | 功能描述:接口—CODEC Portble Stereo CODEC Class H HP Amp RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| CS42L55DNZR | 制造商:Cirrus Logic 功能描述:PORTABLE STEREO CODEC AND UNIQUE CLASS H HP AMP AUTO GRADE & - Tape and Reel |
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