參數(shù)資料
型號: CS42L52-DNZR
廠商: CIRRUS LOGIC INC
元件分類: 消費家電
中文描述: SPECIALTY CONSUMER CIRCUIT, QCC40
封裝: 6 X 6 MM, LEAD FREE, MO-220, QFN-40
文件頁數(shù): 49/59頁
文件大?。?/td> 1800K
代理商: CS42L52-DNZR
DS680F1
53
CS42L52
5/13/08
6.13.4
HP/Speaker De-emphasis
Configures a 15
s/50s digital de-emphasis filter response on the headphone/line and speaker outputs.
6.13.5
Digital Soft Ramp
Configures an incremental volume ramp from the current level to the new level at the specified rate.
Notes:
1.
When the DIGSFT bit is enabled, the Master Volume (MSTxVOL[7:0]) transitions are guaranteed to
occur with a soft ramp only when
bits 7 and 6 in register 29h are set to ‘00’b.
6.13.6
Digital Zero Cross
Configures when the signal level changes occur for the digital volume controls.
Notes:
1.
If the signal does not encounter a zero crossing, the requested volume change will occur after a
timeout period between 1024 and 2048 sample periods (21.3 ms to 42.7 ms at 48 kHz sample rate).
2.
The zero cross function is independently monitored and implemented for each channel.
3.
The DIS_LIMSFT bit (“Limiter Soft Ramp Disable” on page 65) is ignored when zero cross is enabled.
4.
When the DIGSFT bit is enabled, the Master Volume (MSTxVOL[7:0]) transitions are guaranteed to
occur on a zero crossing only when
bits 7 and 6 in register 29h are set to ‘00’b.
DEEMPHASIS
Control Port Status
0
Disabled
1
Enabled
DIGSFT
Volume Changes
Affected Digital Volume Controls
0
Do not occur with a soft ramp
ALC and Limiter Attack/Release (page 66 to page 68)
1
Occur with a soft ramp
Ramp Rate:
1/8 dB every LRCK cycle
DIGZC
Volume Changes
Affected Digital Volume Controls
0
Do not occur on a zero cross-
ing
ALC and Limiter Attack/Release (page 66 to page 68)
1
Occur on a zero crossing
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