參數(shù)資料
型號(hào)： CS5106
廠商： ZF Electronics Corporation
英文描述： Multi-Feature, Synchronous plus Auxiliary PWM Controller
中文描述： 多特征，加上輔助同步PWM控制器
文件頁(yè)數(shù)： 8/12頁(yè)
文件大?。?/td> 195K
代理商： CS5106
C
8
Block Diagram
+
-
+
-
-
C11
+
-
+
A2
-
+
C17
+
-
V
V
V
V
V
V
V
V
V
V
V
V
V
OUVDELAY
OAOUT
OAM
V
SS
Aux. Error Amp
A1
1.2V+
5k
45k
V
CC
D1
Output
Undervoltage
Timer
V
5REF
RAMP1
100k
P1
RUN1
RUN 2
G6
+
-
C9
V
REF
OK
V
FB1
SYNC
IN
PROGRAM
ENABLE
UVSD
SYNC
OUT
DYLSET
FADJ
RAMP2
V
FB2
GATE2
GATE2B
I
LIM2
A2
G1
V
REFOK
Fault Latch
RUN 1
V
SS
G7
G3
C1
G8
FREQ
TOO LOW
Aux.PWM
Comparator
V
REFOK
Comparator
Main PWM
Comparator
Sync Detection
Main 2nd Current
Threshold Comparator
Aux. 2nd Current
Threshold Comparator
Aux. Current
Limit Comparator
Main Current
Limit Comparator
1.2V
V
Skip Two
Clock Pulses
SET
CLOCK
SET
CLOCK
Skip Two
Clock Pulses
G15
C16
Skip2B
G14
G18
1.4V
GATE1
Gnd
I
LIM1
RSFF
Q
F2
R
S
T
PERIOD
DRIVER
+
-
C10
C12
C13
OSC
SYNC
OUT
IFSET
CLK1
CLK2
IDSET
SYNC
IN
+
-
C8
+
-
C5
OVSD
+
-
+
-
G13
C14
G16
G17
C15
DELAY
DELAY
G12
RUN2
RUN2
1.7V
+
DRIVER
Reset
Dominant
G11
G10
G9
VREF
ENABLE
V
REF=
5V
V
CC
5V
-
C2
RSFF
R
S
F1
Q
Set Dominant
+
START
STOP
Over Voltage
Comparator
V
Restart
Comparator
Reset
Dominant
RSFF
R
Q
F3
S
Reset
Dominant
RSFF
Q
F4
S
R
+
-
C4
-
+
C7
Skip2B
ENABLE
Comparator
Under Voltage
Comparator
R
2R
G5
G4
DRIVER
TFF
Q
T1
+
0.13V
0.13V
+
R
2R
RUN1
+
1.5V
C3
+
-
+
-
FREQ
TOO HIGH
1.4V
5V
4.5
7.4/6.8V
1.4V
1.4V
Q
Theory of Application
Powering the IC
The IC has one supply, V
CC
, and one Ground lead. If V
SS
is
used for a bootstrapped supply the diode between V
SS
and
V
CC
is forward biased, and the IC will derive its power
from V
SS
. The internal logic monitors the supply voltage,
V
CC
. During abnormal operating conditions, all GATE
drivers are held in a low state. The CS5106 requires 1.5mA
nominal of startup current.
Startup
Assume the part is enabled and there are no over voltage
or under voltage faults present. Also, assume that all auxil-
iary and main regulated output voltages start at 0V. An
8V, Zener referenced supply is typically applied to V
CC
.
When V
CC
exceeds 7.5V, the 5V reference is enabled and
the OSC begins switching. If the V
5REF
lead is not exces-
sively loaded such that V
5REF
< 4.5V nominal, V
REF
OK
goes high and RUN1 will go high, releasing GATE1
from its low state. After GATE1 is released, it begins
switching according to conditions set by the auxiliary con-
trol loop and the auxiliary supply, V
SS
begins to rise.
When V
SS
> V
CC
+ V(D1), P1 turns on and RUN2 goes
high, releasing GATE2 and GATE2B from their low state.
GATE2 and GATE2B begin switching according to condi-
tions set by the main control loop and the main regulated
output begins to rise. See startup waveforms in Figure 1.
Soft Start
Soft start for the auxiliary power supply is accomplished
by placing a capacitor between OAOUT and Ground. The
error amplifier has 200μA of nominal of source current and
is ideal for setting up a Soft Start condition for the auxiliary
regulator. Care should be taken to make sure that the soft
start timing requirements are not in conflict with any tran-
sient load requirements for the auxiliary supply as large
capacitors on OAOUT will slow down the loop response.
Also, the Soft start capacitor must be chosen such that dur-
ing start or restart, both outputs will come into regulation
before the OUVDELAY timer trips. Soft Start for the main
supply is accomplished by charging soft start capacitor C6
through D5 and R7 at start up. After the main supply has
come into regulation C6 continues to charge and is discon-
nected from the feedback loop by D8.
Theory of Operation
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