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參數(shù)資料
| 型號： | CS5106 |
| 廠商： | ZF Electronics Corporation |
| 英文描述： | Multi-Feature, Synchronous plus Auxiliary PWM Controller |
| 中文描述： | 多特征，加上輔助同步PWM控制器 |
| 文件頁數(shù)： | 9/12頁 |
| 文件大小： | 195K |
| 代理商： | CS5106 |
C
9
Figure 1: Startup waveforms.
Voltage and Current Ramp PWM Comparator Inputs
(V
FB1
,
2
and RAMP1,2 leads)
C10 and C11 are the PWM comparators for the auxiliary
and main supplies. The feedback voltage (V
FB
) is divided
by three and compared with a linear, voltage representa-
tion of the current in the primary side of the transformer
(RAMP). When the output of the feedback comparator
goes high, a reset signal is sent to the PWM flip-flop and
the GATE driver is driven low. A 130mV offset on the
RAMP leads allows the drivers to go to 0% duty cycle in
the presence of light loads.
Feedback Voltage for GATE1 Driver (V
FB1
)
Typically the output of the auxiliary error amplifier (A1) is
tied to V
FB1
. The V
SS
output is programmed to 12V by a
10:1 resistive divider on the negative input of the error
amplifier and a fixed 1.2V reference on the positive input
of the error amplifier.
Pulse by Pulse Over Current Protection and Hiccup
Mode (I
LIM1,2
leads)
C12 and C13 are the pulse by pulse current limit compara-
tors for the auxiliary and main supplies. When the current
in the primary side of the transformer increases such that
the voltage across the current sense resistor exceeds 1.2V
nominal, the output of the current limit comparator goes
high and a reset signal is sent to the PWM flip-flop and
the GATE driver is driven low.
C16 and C17 are the second threshold, pulse by pulse cur-
rent limit comparators for the auxiliary and main supplies.
If the current in the primary side of the transformer
increases so quickly that the current sense voltage is not
limited by C12 or C13 and the voltage across the current
sense resistor exceeds 1.4V, the second threshold compara-
tor will trip a delay circuit and force the GATE driver stage
to go low and stay low for the next two clock cycles.
Undervoltage and Overvoltage Thresholds
C5 and C8 are the undervoltage and overvoltage detection
comparators. Typically, these inputs are tied across the
middle resistor in a three resistor divider with the top
resistor to V
IN
and bottom resistor to Ground. The under
voltage comparator has 200mV of built in hysteresis with
respect to a direct input on the UVSD lead. The under volt-
age comparator has its positive input referenced to 5V
while the over voltage comparator has its negative input
referenced to 5V. The output of both comparators are
ORed at (G4) with the over current and enable inputs. The
output of G4 feeds the input to the fault latch (F2).
PROGRAM and ENABLE Leads
The PROGRAM lead controls the polarity of the ENABLE
lead. If the PROGRAM lead is high or floating, the GATE
outputs will go low if the ENABLE input is tied high or
floating. If the PROGRAM lead is tied low, the GATE out-
puts will go low if the ENABLE input is tied low. If the
part is then enabled after switching the outputs low, the
part will restart according to the procedure outlined in the
òStartupó section.
FAULT Logic
If a V
REF
, UVSD or OVSD fault occurs at any time, G4
resets the fault latch (F2). RUN1 goes low and all gate
drivers cease switching and return to their low state.
When RUN1 goes low, the output of the auxiliary op-amp
(A1) discharges the soft start capacitor and holds it low
while RUN1 is low. If the fault condition is removed before
the OUVDELAY timer is tripped, the IC will restart the
power supplies when V
SS
< 1.4V. If the OUVDELAY timer
trips, the power supply must be restarted as explained in
the following section.
Output Undervoltage Delay Timer for the Main and
Auxiliary Regulated Outputs
C7 and C4 are the output under voltage monitor compara-
tors for the auxiliary and main supplies. If a regulated out-
put drops such that its associated V
FB
voltage exceeds 4.1V,
the output undervoltage monitor comparator goes high
and the OUVDELAY capacitor begins charging from 0V. A
timing relation is set up by a 10μA nominal current source,
the OUVDELAY capacitor and a 5V fault threshold at the
input of C2 (see Figure 2). If any regulated output drops
and stays low for the entire charge time of the OUVDELAY
capacitor, a fault is triggered and all GATE drivers will go
into a low state.
Once this fault is triggered, the IC will restart the power
supplies only if the OUVDELAY fault is reset and ENABLE
or UVSD is toggled while V
SS
< 1.4V. To reset the OUVDE-
LAY fault, both the V
FB
inputs must be less than 4.1V. In
the application circuit shown, V
FB1
is brought low by
OAOUT when RUN1 stops the oscillators. V
FB2
is brought
low when V
AUXP
bleeds down and the V
FB2
opto-isolator is
no longer powered.
Figure 2: OUVDELAY Time vs. OUVDELAY Capacitance
CAPACITANCE (nF)
T
0.01
100
1
0.1
10
1
100
1000
0.1
10
1000
V
SS
> V
CC
7.5V
V
CC
V
REF
,V
REF(OK)
,RUN1
CLK1
GATE1
RAMP1
V
FB1
V
SS
V
FB2
RUN2
CLK2
GATE2
RAMP2
GATE2B
Theory of Application: continued
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