參數(shù)資料
型號： CS5106LSW24
廠商： ZF Electronics Corporation
英文描述： Multi-Feature, Synchronous plus Auxiliary PWM Controller
中文描述： 多特征，加上輔助同步PWM控制器
文件頁數(shù)： 6/12頁
文件大?。?/td> 195K
代理商： CS5106LSW24
Package Lead Description
C
6
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Electrical Characteristics: T
J
= -40C to 125C, V
SS
= 9 to 16V, V
5REF
I
LOAD
= 2mA, SYNC
OUT
Free Running, unless other-
wise specified. For All Specs: UVSD=6V, OVSD = 0V, ENABLE = 0V, I
LIM(1,2)
= 0,V
FB(1,2)
= 3V,R
FADJ
= R
DLYSET
= 27.4k.
PACKAGE LEAD #
LEAD SYMBOL
FUNCTION
I
GATE 2, 2B Non-Overlap Delay
GATE2 Turn-on Delay
from GATE2B
GATE2B Turn-on Delay
from GATE2
Measure delay from GATE2B going low
@1.7V to GATE2 going high @1.7V.
Measure delay from GATE2 going low
@1.7V to GATE2B going high @1.7V.
20.0
45.0
70.0
ns
20.0
45.0
70.0
ns
I
GATE 1, 2, 2B Rise & Fall Times V
SS
=12V,V
CC
=V
SS
-V
DON
GATE1 Rise Time
Measure GATE1 Rise Time from
90% to 10%. C
LOAD
= 150pF.
Measure GATE1 Fall Time from
10% to 90%. C
LOAD
= 150pF.
Measure GATE2 Rise Time from
90% to10%. C
LOAD
= 50pF.
Measure GATE2 Fall Time from
10% to 90%. C
LOAD
= 50pF.
Measure GATE2B Rise Time from
90% to10%. C
LOAD =
50pF.
Measure GATE2B Fall Time from
10% to 90%. C
LOAD
= 50pF.
50.0
80.0
ns
GATE1 Fall Time
30.0
60.0
ns
GATE2 Rise Time
50.0
80.0
ns
GATE2 Fall Time
15.0
30.0
ns
GATE2B Rise Time
50.0
80.0
ns
GATE2B Fall Time
15.0
30.0
ns
1
UVSD
Undervoltage shutdown lead. Typically this lead is connected through a
resistor divider to the main high voltage (V
IN
) line. If the voltage on this lead
is less than 5V then a fault is initiated such that GATE1, GATE2 and GATE2B
go low.
Overvoltage shutdown lead. Typically this lead is connected through a resistor
divider to the main high voltage (V
IN
) line. If the voltage on this lead exceeds
5V then a fault is initiated such that GATE1, GATE2 and GATE2B go low.
5V reference output lead. Capable of 20mA nominal output. If this lead falls
to 4.5V, a fault is initiated such that GATE1, GATE2 and GATE2B go low.
Auxiliary error amplifier minus input. This lead is compared to 1.2V nominal
on the auxiliary error amp plus lead and represents the V
SS
voltage divided
by ten.
Auxiliary error amplifier output lead. Source current 300μA max.
Output undervoltage timing capacitor lead. If the controlled output voltages
of either the main or the auxiliary supply are such that either V
FB1
or V
FB2
is
greater that 4.1V nominal, then capacitor from OUVDELAY to ground will
begin charging. If the over voltage duration is such that the OUVDELAY
voltage exceeds 5V, then a fault will be initiated such that GATE1, GATE2
and GATE2B will go low.
Pulse by pulse over current protection lead for the auxiliary PWM. A voltage
exceeding 1.2V nominal on I
LIM1
will cause GATE1 to go low. A voltage
exceeding 1.4V nominal on I
LIM1
will cause GATE1 to go low for at least two
clock cycles.
Current Ramp Input Lead for the Auxiliary PWM. A voltage which is linear
with respect to current in the primary side of the auxiliary trans former is
usually represented on this lead. A voltage exceeding V
FB1
- 0.13 on RAMP1
will cause GATE1 to go low.
2
OVSD
3
V
5REF
4
OAM
5
6
OAOUT
OUVDELAY
7
I
LIM1
8
RAMP1
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