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參數(shù)資料
| 型號： | CS51311GDR14 |
| 廠商： | ZF Electronics Corporation |
| 英文描述： | Synchronous CPU Buck Controller for 12V and 5V Applications |
| 中文描述： | 同步降壓控制器的CPU為12V和5V的應(yīng)用 |
| 文件頁數(shù)： | 14/19頁 |
| 文件大?。?/td> | 239K |
| 代理商： | CS51311GDR14 |
Application Information: continued
C
14
C
DG
(I
GATE
= C
dg
dV
dg
/dt). Unless the gate-drive
impedance is very low, the V
GS
waveform commonly
plateaus during rapid changes in the drain-to-source volt-
age.
The most important aspect of FET performance is the Static
Drain-To-Source On-Resistance (R
DS(ON)
), which effects
regulator efficiency and FET thermal management require-
ments. The On-Resistance determines the amount of cur-
rent a FET can handle without excessive power dissipation
that may cause overheating and potentially catastrophic
failure. As the drain current rises, especially above the con-
tinuous rating, the On-Resistance also increases. Its posi-
tive temperature coefficient is between +0.6%/C and
+0.85%/C. The higher the On-Resistance the larger the
conduction loss is. Additionally, the FET gate charge
should be low in order to minimize switching losses and
reduce power dissipation.
Both logic level and standard FETs can be used. The refer-
ence designs derive gate drive from the 12V supply, which
is generally available in most computer systems and uti-
lizes logic level FETs.
Voltage applied to the FET gates depends on the applica-
tion circuit used. Both upper and lower gate driver outputs
are specified to drive to within 1.5V of ground when in the
low state and to within 2V of their respective bias supplies
when in the high state. In practice, the FET gates will be
driven rail-to-rail due to overshoot caused by the capaci-
tive load they present to the controller IC.
Step 7a - Selection of the switching (upper) FET
The designer must ensure that the total power dissipation
in the FET switch does not cause the power component’s
junction temperature to exceed 150°C.
The maximum RMS current through the switch can be
determined by the following formula:
I
RMS(H)
=
,
where
I
RMS(H)
= maximum switching MOSFET RMS current;
I
L(PEAK)
= inductor peak current;
I
L(VALLEY)
= inductor valley current;
D = Duty Cycle.
Once the RMS current through the switch is known, the
switching MOSFET conduction losses can be calculated:
P
RMS(H)
= I
RMS(H)2
×
R
DS(ON)
where
P
RMS(H)
= switching MOSFET conduction losses;
I
RMS(H)
= maximum switching MOSFET RMS current;
R
DS(ON)
= FET drain-to-source on-resistance
The upper MOSFET switching losses are caused during
MOSFET switch-on and switch-off and can be determined
by using the following formula:
P
SWH
= P
SWH(ON)
+ P
SWH(OFF)
=
,
where
P
SWH(ON)
= upper MOSFET switch-on losses;
P
SWH(OFF)
= upper MOSFET switch-off losses;
V
IN
= input voltage;
I
OUT
= load current;
t
RISE
= MOSFET rise time (from FET manufacturer’s
switching characteristics performance curve);
t
FALL
= MOSFET fall time (from FET manufacturer’s
switching characteristics performance curve);
T = 1/F
SW
= period.
The total power dissipation in the switching MOSFET can
then be calculated as:
P
HFET(TOTAL)
= P
RMSH
+ P
SWH(ON)
+ P
SWH(OFF)
,
where
P
HFET(TOTAL)
= total switching (upper) MOSFET losses;
P
RMSH
= upper MOSFET switch conduction Losses;
P
SWH(ON)
= upper MOSFET switch-on losses;
P
SWH(OFF)
= upper MOSFET switch-off losses.
Once the total power dissipation in the switching FET is
known, the maximum FET switch junction temperature
can be calculated:
T
J
= T
A
+ [P
HFET(TOTAL)
×
R
θ
JA
],
where
T
J
= FET junction temperature;
T
A
= ambient temperature;
P
HFET(TOTAL)
= total switching (upper) FET losses;
R
θ
JA
= upper FET junction-to-ambient thermal resistance
Step 7b: Selection of the synchronous (lower) FET
The switch conduction losses for the lower FET can be cal-
culated as follows:
P
RMSL
= I
RMS2
×
R
DS(ON)
= [I
OUT
×
(1
D)]
2
×
R
DS(ON)
,
where
P
RMSL
= lower MOSFET conduction losses;
I
OUT
= load current;
D = Duty Cycle;
R
DS(ON)
= lower FET drain-to-source on-resistance.
The synchronous MOSFET has no switching losses, except
for losses in the internal body diode, because it turns on
into near zero voltage conditions. The MOSFET body
diode will conduct during the non-overlap time and the
resulting power dissipation (neglecting reverse recovery
losses) can be calculated as follows:
P
SWL
= V
SD
×
I
LOAD
×
non-overlap time
×
F
SW
,
where
P
SWL
= lower FET switching losses;
V
SD
= lower FET source-to-drain voltage;
I
LOAD
= load current
Non-overlap time = GATE(L)-to-GATE(H) or GATE(H)-
to-GATE(L) delay (from CS51311 data sheet Electrical
V
IN
×
I
OUT
×
(t
RISE
+ t
FALL
)
6T
(I
L(PEAK)2
+ (I
L(PEAK)
×
I
L(VALLEY)
) + I
L(VALLEY)2
×
D
3
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