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參數(shù)資料
| 型號： | CS51312 |
| 廠商： | ZF Electronics Corporation |
| 英文描述： | Synchronous CPU Buck Controller for 12V Only Applications |
| 中文描述： | 同步降壓控制器的CPU，只有應(yīng)用的12V |
| 文件頁數(shù)： | 15/18頁 |
| 文件大?。?/td> | 276K |
| 代理商： | CS51312 |
Application Information: continued
15
C
Step 8: Control IC Power Dissipation
The power dissipation of the IC varies with the MOSFETs
used, V
CC
, and the CS51312 operating frequency. The aver-
age MOSFET gate charge current typically dominates the
control IC power dissipation.
The IC power dissipation is determined by the formula:
P
CONTROLIC
= I
CC1
V
CC1
+ P
GATE(H)
+ P
GATE(L)
,
where
P
CONTROLIC
= control IC power dissipation;
I
CC1
= IC quiescent supply current;
V
CC1
= IC supply voltage;
P
GATE(H)
= upper MOSFET gate driver (IC) losses;
P
GATE(L)
= lower MOSFET gate driver (IC) losses.
The upper (switching) MOSFET gate driver (IC) losses are:
P
GATE(H)
= Q
GATE(H)
×
F
SW
×
V
GATE(H)
,
where
P
GATE(H)
= upper MOSFET gate driver (IC) losses;
Q
GATE(H)
= total upper MOSFET gate charge;
F
SW
= switching frequency;
V
GATE(H)
= upper MOSFET gate voltage.
The lower (synchronous) MOSFET gate driver (IC) losses
are:
P
GATE(L)
= Q
GATE(L)
×
F
SW
×
V
GATE(L)
,
where
P
GATE(L)
= lower MOSFET gate driver (IC) losses;
Q
GATE(L)
= total lower MOSFET gate charge;
F
SW
= switching frequency;
V
GATE(L)
= lower MOSFET gate voltage.
The junction temperature of the control IC is primarily a
function of the PCB layout, since most of the heat is
removed through the traces connected to the pins of the IC.
Step 9: Slope Compensation
Voltage regulators for today’s advanced processors are
expected to meet very stringent load transient require-
ments. One of the key factors in achieving tight dynamic
voltage regulation is low ESR at the CPU input supply
pins. Low ESR at the regulator output results in low output
voltage ripple. The consequence is, however, that there’s
very little voltage ramp at the control IC feedback pin (V
FB
)
and regulator sensitivity to noise and loop instability are
two undesirable effects that can surface. The performance
of the CS51312-based CPU V
CC(CORE)
regulator is
improved when a fixed amount of slope compensation is
added to the output of the PWM Error Amplifier (COMP
pin) during the regulator Off-Time. Referring to Figure 12,
the amount of voltage ramp at the COMP pin is dependent
on the gate voltage of the lower (synchronous) FET and the
value of resistor divider formed by R1and R2.
V
SLOPECOMP
= V
GATE(L)
×
(
)
×
(1
e ),
where
V
SLOPECOMP
= amount of slope added;
V
GATE(L)
= lower MOSFET gate voltage;
R1, R2 = voltage divider resistors;
t = t
ON
or t
OFF
(switch off-time);
τ
= RC constant determined by C1 and the parallel com-
bination of R1, R2 (Figure 12), neglecting the low driver
output impedance.
Figure 12: Small RC filter provides the proper voltage ramp at the begin-
ning of each on-time cycle.
The artificial voltage ramp created by the slope compensa-
tion scheme results in improved control loop stability pro-
vided that the RC filter time constant is smaller than the
off-time cycle duration (time during which the lower MOS-
FET is conducting). It is important that the series combina-
tion of R1 and R2 is high enough in resistance to avoid
loading the GATE(L) pin.
Step 10: Selection of Current Limit Filter Components
In some applications, the current limit comparator may
falsely trigger due to noise, load transients, or high induc-
tor ripple currents. A filter circuit such as the one shown in
Figure 13 can be added to prevent this. The RC time con-
stant of this filter is equal to (R
FB
+ R
OUT
)
×
C
SENSE
.
Increasing the RC time constant will reduce the sensitivity
of the circuit, but increase the time required to detect an
overcurrent condition. The value of R
FB
+ R
OUT
should be
kept to 510
or lower to avoid significant DC offsets due
to the V
FB
and V
OUT
bias currents.
Figure 13: Current limit filter circuit.
Adaptive voltage positioning is used to help keep the out-
put voltage within specification during load transients. To
implement adaptive voltage positioning a “Droop
Resistor” must be connected between the output inductor
“Droop” Resistor for Adaptive Voltage Positioning
and Current Limit
+
GATE(H)
GATE(L)
V
FB
V
OUT
V
IN
R
SENSE
V
OUT
R
FB
R
OUT
C
SENSE
C
COMP
R
1
To Synchronous FET
C
1
R
2
16
12
COMP
GATE(L)
CS51312
-t
R2
R1 + R2
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|---|---|
| CS51312GD16 | Synchronous CPU Buck Controller for 12V Only Applications |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CS-51313D16 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Current-Mode SMPS Controller |
| CS-51313DR16 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Current-Mode SMPS Controller |
| CS51313GDR16 | 制造商:Rochester Electronics LLC 功能描述: 制造商:ON Semiconductor 功能描述: |
| CS-5132 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Dual Output CPU Buck Controller |
| CS5132DW24 | 制造商:ON Semiconductor 功能描述: |
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