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參數(shù)資料
| 型號： | CS5332GDW28 |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 1.5 A SWITCHING CONTROLLER, 1000 kHz SWITCHING FREQ-MAX, PDSO28 |
| 封裝： | SOP-28 |
| 文件頁數(shù)： | 8/20頁 |
| 文件大小： | 400K |
| 代理商： | CS5332GDW28 |
CS5332
http://onsemi.com
16
DESIGN PROCEDURE
Current Sensing, Power Stage and
Output Filter Components
1. Choose the output filter components to meet peak
transient requirements. The formula below can be
used to provide an approximate starting point for
capacitor choice, but will be inadequate to calculate
actual values.
DVPEAK + (DI DT)
ESL ) DI
ESR
Ideally the output filter should be simulated with
models including ESR, ESL, circuit board parasitics
and delays due to switching frequency and converter
response.
Typically
both
bulk
capacitance
(electrolytic, Oscon, etc,) and low impedance
capacitance (ceramic chip) will be required. The bulk
capacitance provides “hold up” during the converter
response. The low impedance capacitance reduces
steady state ripple and bypasses the bulk capacitance
during slewing of output current.
2. For inductive current sensing (only) choose the
current sense network RC to provide a 25 mV
minimum ramp during steady state operation.
R + (VIN * VOUT)
VOUT VIN
F
C
25 mV
Then choose the inductor value and inherent resistance
to satisfy L/RL = R × C.
For ideal current sense compensation the ratio of L and
RL is fixed, so the values of L and RL will be a
compromise typically with the maximum value RL
limited by conduction losses or inductor temperature
rise and the minimum value of L limited by ripple
current.
3. For resistive current sensing choose L and RS to
provide a steady state ramp greater than 25 mV.
L RS + (VIN * VOUT)
TON 25 mV
Again the ratio of L and RL is fixed and the values of
L and RS will be a compromise.
4. Calculate the high frequency output impedance
(ConverterZ) of the converter during transients. This
is the impedance of the Output filter ESR in parallel
with the power stage output impedance (PwrstgZ)
and will indicate how far from the original level
(ΔVR) the output voltage will typically recover to
within one switching cycle. For a good transient
response ΔVR should be less than the peak output
voltage overshoot or undershoot.
DVR + ConverterZ
ESR
ConverterZ +
PwrstgZ
ESR
PwrstgZ ) ESR
where:
PwrstgZ + RS
CSA Gain 2.0
Multiply the converterZ by the output current step size
to calculate where the output voltage should recover to
within the first switching cycle after a transient. If the
ConverterZ is higher than the value required to recover
to where the adaptive positioning is set, the remainder
of the recovery will be controlled by the error amp
compensation and will typically recover in 10 20 μs.
DVR + DIOUT
ConverterZ
Make sure that ΔVR is less than the expected peak
transient for a good transient response.
5. Adjust L and RL or RS as required to meet the best
combination of transient response, steady state output
voltage ripple and pulse width jitter.
Current Limit
When the sum of the Current Sense amplifiers (VITOTAL)
exceeds the voltage on the ILIM pin the part will enter hiccup
mode. For inductive sensing the ILIM pin voltage should be
set based on the inductor resistance (or current sense
resistor) at max temperature and max current. To set the level
of the ILIM pin:
6. VI(LIM) + R IOUT(LIM) CS to ILIM Gain
where:
R is RL or RS;
IOUT(LIM) is the current limit threshold.
For the overcurrent to work properly the inductor time
constant (L/R) should be ≤ the Current sense RC. If the
RC is too fast, during step loads the current waveform
will appear larger than it is (typically for a few hundred
μs) and may trip the current limit at a level lower than
the DC limit.
Adaptive Positioning
7. To set the amount of voltage positioning below the
DAC setting at no load, connect a resistor (RV(FB))
between the output voltage and the VFB pin. Choose
RV(FB) as;
RV(FB) + NL Position VFB Bias Current
8. To set the difference in output voltage between no
load and full load, connect a resistor (RV(DRP))
between the VDRP and VFB pins. RV(DRP) can be
calculated in two steps. First calculate the difference
between the VDRP and VFB pin at full load. (The VFB
voltage should be the same as the DAC voltage during
closed loop operation.) Then choose the RV(DRP) to
source enough current across RV(FB) for the desired
change in output voltage.
DVV(DRP) + IOUTFL
R
CS to VDRP Gain
where:
R = RL or RS for one phase;
IOUTFL is the full load output current.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| CS5332GDWR28 | 功能描述:IC REG CTRLR BUCK PWM 28-SOIC RoHS:否 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - DC DC 切換控制器 系列:- 標(biāo)準(zhǔn)包裝:4,000 系列:- PWM 型:電壓模式 輸出數(shù):1 頻率 - 最大:1.5MHz 占空比:66.7% 電源電壓:4.75 V ~ 5.25 V 降壓:是 升壓:無 回掃:無 反相:無 倍增器:無 除法器:無 Cuk:無 隔離:無 工作溫度:-40°C ~ 85°C 封裝/外殼:40-VFQFN 裸露焊盤 包裝:帶卷 (TR) |
| CS5333 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:24-Bit, 96 kHz Stereo A/D Converter |
| CS5333-BZ | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CS5333-KZ | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:24-Bit, 96 kHz Stereo A/D Converter |
| CS5333-KZR | 制造商:Cirrus Logic 功能描述: |
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