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參數(shù)資料
| 型號(hào)： | CS5373A-ISZR |
| 廠商： | Cirrus Logic Inc |
| 文件頁數(shù)： | 15/40頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC/MODULATOR LP/HP 28-SSOP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 類型： | 調(diào)制器 |
| 分辨率（位）： | 24 b |
| 采樣率（每秒）： | 512k |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 電源電壓： | ± 2.5V，3.3V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SSOP（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-SSOP |
| 包裝： | 帶卷 (TR) |
| 配用： | CDB5378-ND - EVALUATION BOARD FOR CS5378 |
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CS5373A
22
DS703F2
5. OPERATIONAL MODES
The CS5373A has seven operational modes
and one sleep mode selected by the MODE2,
MODE1, and MODE0 pins.
5.1 Modulator Mode
Modulator mode (MODE 0) enables the
ΔΣ
modulator and disables the DAC AC and DC
test circuitry to save power. This mode is used
for normal sensor measurements after self-
tests are completed.
5.1.1
Modulator One’s Density
In modulator mode (and whenever the modu-
lator is enabled) the differential analog input
signal is converted to an oversampled
ΔΣ seri-
al bit stream on the MDATA output, with a
one’s density proportional to the differential
amplitude of the analog input signal.
One’s density of the MDATA output is defined
as the ratio of ‘1’ bits to total bits in the serial
bit stream output, i.e. an 86% one’s density
has, on average, a ‘1’ value in 86 of every 100
output data bits. The MDATA output has a
nominal 50% one’s density for a mid-scale dif-
ferential input, approximately 86% one’s den-
sity
for
a
positive
full-scale
input,
and
approximately 14% one’s density for a nega-
tive full-scale input.
5.1.2
Modulator Decimated Output
When the CS5373A modulator operates with
the CS5378 digital filter, the final decimated,
24-bit, full-scale output code range depends if
digital offset correction is enabled. With digital
offset correction enabled, amplifier offset and
the modulator internal offset are removed from
the final conversion result.
5.1.3
Modulator Synchronization
The modulator is designed to operate synchro-
nously with other modulators in a measure-
ment network, so a rising edge on the MSYNC
input resets the internal conversion state ma-
chine to synchronize analog sample timing.
MSYNC is automatically generated by the
CS5378 digital filter after receiving a synchro-
nization signal from the external system, and
is chip-to-chip accurate within ± 1 MCLK peri-
od.
Table 2. Operational Modes
Modes of Operation
Selection
MODE
[2:0]
Mode Description
00 0 0
Modulator: enabled.
DAC: sleep.
10 0 1
Modulator: enabled.
DAC: AC OUT and BUF outputs.
20 1 0
Modulator: enabled.
DAC: AC OUT only, BUF high-z.
30 1 1
Modulator: enabled.
DAC: AC BUF only, OUT high-z.
41 0 0
Modulator: enabled.
DAC: DC common mode output.
51 0 1
Modulator: enabled.
DAC: DC differential output.
61 1 0
Modulator: enabled.
DAC: AC common mode output.
71 1 1
Modulator: sleep.
DAC: sleep.
Table 3. Output Coding for the CS5373A
Modulator and CS5378 Digital Filter Combination
Modulator
Differential Analog
Input Signal
CS5378 Digital Filter
Output Code
Offset
Corrected
+100 mV
Offset
> + (VREF + 5%)
Error Flag Possible
+ VREF
5D1C41
60D5B4
0 V
000000
03B973
- VREF
A2EAAE
A6A421
> - (VREF + 5%)
Error Flag Possible
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