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參數(shù)資料
| 型號： | CS5373A-ISZR |
| 廠商： | Cirrus Logic Inc |
| 文件頁數(shù)： | 28/40頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC/MODULATOR LP/HP 28-SSOP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 類型： | 調(diào)制器 |
| 分辨率（位）： | 24 b |
| 采樣率（每秒）： | 512k |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 電源電壓： | ± 2.5V，3.3V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SSOP（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-SSOP |
| 包裝： | 帶卷 (TR) |
| 配用： | CDB5378-ND - EVALUATION BOARD FOR CS5378 |
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CS5373A
34
DS703F2
9.4 SCR Latch-up
The VA- pin is tied to the CS5373A CMOS
substrate and must always be the most-nega-
tive voltage applied to the device to ensure
SCR latch-up does not occur. In general,
latch-up may occur when any pin voltage ex-
ceeds
the
limits
specified
in
the
Absolute Maximum Ratings table.
It is recommended to connect the VA- power
supply to system ground (GND) with a re-
verse-biased Schottky diode. At power up, if
the VA+ power supply ramps before the VA-
supply is established, the VA- pin voltage
could be pulled above ground potential
through the CS5373A device. If the VA- supply
is pulled 0.7 V or more above GND, SCR
latch-up can occur. A reverse-biased Schottky
diode will clamp the VA- voltage a maximum of
0.3 V above ground to ensure SCR latch-up
does not occur at power up.
9.5 DC-DC Converters
Many low-frequency measurement systems
are battery powered and utilize DC-DC con-
verters to efficiently generate power supply
voltages. To minimize interference effects, op-
erate the DC-DC converter at a frequency
which is rejected by the digital filter, or operate
it synchronous to the MCLK rate.
A synchronous DC-DC converter whose oper-
ating frequency is derived from MCLK will the-
oretically minimize the potential for “beat
frequencies” to appear in the measurement
bandwidth. However this requires the source
clock to remain jitter-free within the DC-DC
converter circuitry. If clock jitter can occur with-
in the DC-DC converter (as in a PLL-based ar-
chitecture),
it’s
better
to
use
a
non-
synchronous DC-DC converter whose switch-
ing frequency is rejected by the digital filter.
During PCB layout, do not place high-current
DC-DC converters near sensitive analog com-
ponents. Carefully routing a separate DC-DC
“star” ground will help isolate noisy switching
currents away from the sensitive analog com-
ponents.
10.TERMINOLOGY
Signal-to-Noise Ratio (Dynamic Range) - Ratio of the rms magnitude of the full-scale signal to the integrated
rms noise from DC to 400 Hz. The following formula is used to calculate SNR:
Total Harmonic Distortion - Ratio of the power of the fundamental frequency to the sum of the powers of all
harmonic frequencies from DC to 400 Hz. The following formula is used to calculate THD:
Full-scale Bandwidth - The bandwidth in which the converter can generate a full-scale signal while maintaining
performance specifications.
Impulse Amplitude - The maximum amplitude of the output signal beyond the full-scale bandwidth.
Differential Output Level - The voltage between the analog output pins of the device.
SNR = 20log
rms magnitude of full scale signal
rms magnitude of noise floor
(
THD = 10log
power of the fundamental frequency
sum of the powers of the harmonic frequencies
(
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