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參數(shù)資料
| 型號： | CS5513-BSZ |
| 廠商： | Cirrus Logic Inc |
| 文件頁數(shù)： | 8/26頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 20BIT INTERNAL OSC 8SOIC |
| 標(biāo)準(zhǔn)包裝： | 100 |
| 位數(shù)： | 20 |
| 采樣率（每秒）： | 326 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 2.7mW |
| 電壓電源： | 雙 ± |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SOIC |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 1 個差分，雙極 |
| 產(chǎn)品目錄頁面： | 755 (CN2011-ZH PDF) |
| 其它名稱： | 598-1707 |
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CS5510/11/12/13
16
DS337F4
2.5.1
Reading Conversions -
CS5510/12
After power-up, the CS5510/12 will begin convert-
ing once a clock source is applied to the SCLK pin.
When a conversion has completed, and there is
new data in the output register, the SDO line will
fall to a logic-low level if CS is also at a logic-low
state (SDO will always be high-impedance when
CS is high). If CS is low at the end of the conver-
sion cycle, SDO will fall on the rising edge of an
SCLK. After SCLK falls, the next SCLK cycle (high,
then low) will begin clocking out the data. The first
data bit therefore, is 1-
SCLK cycles wide. Twen-
ty-four SCLK cycles (after the initial high-low tran-
sition) are needed to retrieve the conversion word
bits can be read on the rising edge of SCLK, and
the next data bit is output to SDO on the falling
edge of SCLK. Once the entire data word has been
read, SDO will return to a logic-high state until
there is a new conversion word available. If CS is
at a logic-high at the end of the conversion cycle,
the data will not be shifted out of the part until CS
is brought to a logic-low state during the next con-
version cycle. If a new conversion becomes avail-
able while the current data is being read, the data
register will not be updated, and the new conver-
sion word will be lost. The user need not read every
conversion. If the user chooses not to read a con-
version, CS should remain at a logic-high state for
the duration of the conversion cycle. Note that if
CS goes to a logic-high state during a read, the
current conversion data will be lost and replaced
by a new conversion word when the new conver-
sion data is available.
2.5.2
Reading Conversions -
CS5511/13
After power-up, the CS5511/13 begins converting
and updating the output register. When there is
new data in the output register (at the end of a con-
version cycle) the SDO line will fall to a logic-low
level if CS is also at a logic-low state (SDO will al-
ways be high-impedance when CS is high). Twen-
ty-four SCLK cycles are needed to retrieve the
conversion word from the device (see Figures 18
and 19). The data bits can be read on the rising
edge of SCLK, and the next data bit is output to
SDO on the falling edge of SCLK. Once the entire
data word has been read, SDO will return to a log-
ic-high state until there is a new conversion word
available. If new conversions become available
while the current data is being read, the data regis-
ter will not be updated, and the new conversions
will be lost. The user need not read every conver-
sion. If the user chooses not to read a conversion
after SDO falls, SDO will rise seventeen oscillator
clock cycles (of the internal oscillator) before the
next conversion word is available and then fall
again to signal that the conversion is complete.
Note that if a conversion word is not read before
the next conversion word is ready, or if CS goes to
a logic-high state during a read, the current conver-
sion data will be lost and replaced by a new con-
version word when the new conversion data is
available.
SD O
SC L K
Da ta T im e
24 S C LK s
MS B
LSB
CS
0
OF
OD
0
00
0
Figure 16. Data Word Timing for the CS5510.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CS5513-BSZR | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC IC 20-Bit 8-Pin Delta Sigma ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| CS5516 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:16BIT/20-BIT BRIDGE TRANSDUCER A/D CONVERTER |
| CS5516-AP | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 16-Bit Bridge Transducer ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| CS5516-APZ | 制造商:Cirrus Logic 功能描述: |
| CS5516-AS | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 16-Bit Bridge Transducer ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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