參數(shù)資料
型號: CS5513-BSZ
廠商: Cirrus Logic Inc
文件頁數(shù): 9/26頁
文件大小: 0K
描述: IC ADC 20BIT INTERNAL OSC 8SOIC
標(biāo)準(zhǔn)包裝: 100
位數(shù): 20
采樣率(每秒): 326
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 2.7mW
電壓電源: 雙 ±
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-SOIC(0.209",5.30mm 寬)
供應(yīng)商設(shè)備封裝: 8-SOIC
包裝: 管件
輸入數(shù)目和類型: 1 個差分,雙極
產(chǎn)品目錄頁面: 755 (CN2011-ZH PDF)
其它名稱: 598-1707
CS5510/11/12/13
DS337F4
17
2.5.3
Output Coding
As shown in Tables 1 and 2, the CS5510/11/12/13
present output conversions as 24-bit conversion
words. The first bit of the conversion word indi-
cates that a conversion is done through SDO fall-
ing from a logic high to a logic low level. The first
and the fourth bits output will always be zero. The
second and third bits are error flags, representing
an overflow or oscillation condition. In the
CS5510/11, there are four more bits of zero, and
the remaining 16 bits are the conversion data, out-
put MSB first (Table 2). In the CS5512/13, the final
20 bits are the conversion data, which is output
MSB first (Table 1).
Bits D22-D21 are the two flag bits. The OF (Over-
range Flag) bit is set to a logic 1 any time the input
signal is more positive than positive full scale, or
more negative than negative full scale. It is cleared
back to logic 0 whenever a conversion word occurs
which is not overranged. The OD (Oscillation De-
tect) bit is set to a logic 1 any time that an oscillatory
condition is detected in the modulator.
This does
not occur under normal operating conditions, but
may occur whenever the input to the converter is ex-
SD O
SC L K
D a ta T im e
24 S C L K s
MS B
LS B
CS
0
OF
OD
0
00
0
Figure 17. Data Word Timing for the CS5511.
SDO
SC L K
D a ta T im e
24 S C LK s
MS B
LSB
CS
0
OF
O D
0
Figure 18. Data Word Timing for the CS5512.
SD O
SC L K
Da ta T im e
24 S C LK s
MS B
LS B
CS
0
OF
O D
0
Figure 19. Data Word Timing for the CS5513.
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