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參數(shù)資料
| 型號： | CX72302-11 |
| 廠商： | SKYWORKS SOLUTIONS INC |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 6100 MHz, PDSO28 |
| 封裝： | EXPOSED PAD, TSSOP-28 |
| 文件頁數(shù)： | 15/20頁 |
| 文件大?。?/td> | 162K |
| 代理商： | CX72302-11 |
DATA SHEET CX72302
Skyworks Solutions, Inc. Phone [781] 376-3000 Fax [781] 376-3100 sales@skyworksinc.com www.skyworksinc.com
4
July 22, 2004 Skyworks Proprietary and Confidential information Products and Product Information are Subject to Change Without Notice 101216G
Power Down
The CX72302 supports a number of power-down modes through
the serial interface. For more information, see the Register
Descriptions section of this document.
Operation
This section describes the operation of the CX72302. The serial
interface is described first, followed by information on how to
obtain values for the Divide Ratio Registers.
Serial Interface
The serial interface consists of three pins: Clock (pin 1), Data
(pin 27), and CS (pin 28). The Clock signal controls data on the
two serial data lines (Data and CS). The Data pin bits shift into a
temporary register on the rising edge of Clock. The CS line allows
individual selection transfers that synchronize and sample the
information of slave devices on the same bus.
Figure 3 functionally depicts how a serial transfer takes place.
A serial transfer is initiated when a microcontroller or
microprocessor forces the CS line to a low state. This is followed
immediately by an address/data stream sent to the Data pin that
coincides with the rising edges of the clock presented on the
Clock line.
Each rising edge of the Clock signal shifts in one bit of data on the
Data line into a shift register. At the same time, one bit of data is
shifted out of the Mux_out pin (if the serial bit stream is selected)
at each falling edge of Clock. To load any of the synthesizer
registers, 16 bits of address or data must be presented to the
Data line with the data LSB last while CS is low. If CS is low for
more than 16 clock cycles, only the last address or data bits are
used to load the synthesizer registers.
If the CS line is brought to a high state before the 13th clock edge
on Clock, the bit stream is assumed to be modulation data
samples. In this case, it is assumed that no address bits are
present and that all the bits in the stream should be loaded into
the Modulation Data Register.
Synthesizer Register Programming
Synthesizer register programming equations, described in this
section, use the following variables and constants:
Nfractional
Desired VCO division ratio in fractional-N applications.
This is a real number and can be interpreted as the
reference frequency (Fref) multiplying factor such that
the resulting frequency is equal to the desired VCO
frequency.
Ninteger
Desired VCO division ratio in integer-N applications.
This number is an integer and can be interpreted as
the reference frequency (Fref) multiplying factor so that
the resulting frequency is equal to the desired VCO
frequency.
Nreg
9-bit unsigned input value to the divider ranging from
0 to 511 (integer-N mode) and from 6 to 505
(fractional-N mode).
divider
This constant equals 262144 when the
Σ modulator
is in 18-bit mode, and 1024 when the
Σ modulator is
in 10-bit mode.
dividend
When in 18-bit mode, this is the 18-bit signed input
value to the
Σ modulator, ranging from
–131072 to +131071 and providing 262144 steps,
each of Fdiv_ref/218 Hz.
When in 10-bit mode, this is the 10-bit signed input
value to the
Σ modulator, ranging from
–512 to +511 and providing 1024 steps, each of
Fdiv_ref/210 Hz.
FVCO
Desired VCO frequency (either Fvco_main or Fvco_aux).
Fdiv_ref
Divided reference frequency presented to the phase
detector (either Fref_main or Fref_aux).
X
A3
A2
A1
A0
D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
XXX
Clock
Last
Data
CS
C1413
Figure 3. Serial Transfer Timing Diagram
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