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參數(shù)資料
| 型號： | CX72302-11 |
| 廠商： | SKYWORKS SOLUTIONS INC |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 6100 MHz, PDSO28 |
| 封裝： | EXPOSED PAD, TSSOP-28 |
| 文件頁數(shù)： | 2/20頁 |
| 文件大?。?/td> | 162K |
| 代理商： | CX72302-11 |
DATA SHEET CX72302
Skyworks Solutions, Inc. Phone [781] 376-3000 Fax [781] 376-3100 sales@skyworksinc.com www.skyworksinc.com
10
July 22, 2004 Skyworks Proprietary and Confidential information Products and Product Information are Subject to Change Without Notice 101216G
C1418
A3
A2 A1
A0 11
10
9
8
7
6
5
4
3
2
1
0
00
01
X
X MSB
LSB
Main Synthesizer Dividend (MSBs)
Figure 7. Main Dividend MSB Register (Write Only)
A3
A2 A1
A0
11
10
9
8
7
6
5
4
3
2
1
0
00
10
X
MSB
LSB
Main Synthesizer Dividend (LSBs)
C1419
Figure 8. Main Dividend LSB Register (Write Only)
A3
A2 A1
A0
11
10
9
8
7
6
5
4
3
2
1
0
00
11
X
X MSB
LSB
Auxiliary Synthesizer Divider Index
C1420
Figure 9. Auxiliary Divider Register (Write Only)
Auxiliary Synthesizer Registers. The Auxiliary Divider Register
contains the integer portion closest to the desired fractional-N (or
integer-N) value minus 32 for the auxiliary synthesizer. This
register, in conjunction with the Auxiliary Dividend Register, which
controls the fraction offset (from –0.5 to +0.5) allows selection of
a precise frequency. As shown in Figure 9, the value to be loaded
is:
Auxiliary Synthesizer Divider Index = 9-bit value for the integer
portion of the auxiliary synthesizer dividers. Valid values for this
register are from 6 to 505 (fractional-N) or from 0 to 511
(integer-N).
The Auxiliary Dividend Register controls the fraction part of the
desired fractional-N value and allows an offset of –0.5 to +0.5 to
the auxiliary integer selected through the Auxiliary Divider
Register. As shown in Figure 10, the value to be loaded is:
Auxiliary Synthesizer Dividend = 10-bit value for the dividend
for the auxiliary synthesizer.
For information on programming and loading order for these
registers, refer to the Operation section of this document.
General Synthesizer Registers. The Reference Frequency
Dividers Register configures the dual-programmable reference
frequency dividers for the main and auxiliary synthesizers.
The dual-programmable reference frequency dividers provide the
reference frequencies to the phase detectors by dividing the
crystal oscillator frequency. The lower five bits hold the reference
frequency divide index for the main phase detector. The next five
bits hold the reference frequency divide index for the auxiliary
phase detector. Divide ratios from 1 to 32 are possible for each
reference frequency divider (see Tables 2 and 3). As shown in
Figure 11, the values to be loaded are:
Main Reference Frequency Divider Index = Desired main
oscillator frequency division ratio –1. Default value on power-up
is 0, signifying that the reference frequency is not divided for
the main phase detector.
Auxiliary Reference Frequency Divider Index = Desired auxiliary
oscillator frequency division ratio –1. Default value on power-up
is 0, signifying that the reference frequency is not divided for
the auxiliary phase detector.
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