參數(shù)資料
型號: CX72302-11
廠商: SKYWORKS SOLUTIONS INC
元件分類: PLL合成/DDS/VCOs
英文描述: PLL FREQUENCY SYNTHESIZER, 6100 MHz, PDSO28
封裝: EXPOSED PAD, TSSOP-28
文件頁數(shù): 16/20頁
文件大?。?/td> 162K
代理商: CX72302-11
DATA SHEET CX72302
Skyworks Solutions, Inc. Phone [781] 376-3000 Fax [781] 376-3100 sales@skyworksinc.com www.skyworksinc.com
101216G Skyworks Proprietary and Confidential information Products and Product Information are Subject to Change Without Notice July 22, 2004
5
Fractional-N Applications. The desired division ratio for the
main synthesizer is given by:
Nfractional
F
VCO_mai n
4F
di v_ref
---------------------------------
=
The desired division ratio for the auxiliary synthesizer is given by:
Nfractional
F
VCO_aux
F
di v_ref
-------------------------
=
where Nfractional must be between 150 and 2150 for the main
synthesizer or between 37.5 and 537.5 for the auxiliary
synthesizer.
The value to be programmed in the Main or Auxiliary Divider
Register is given by:
32
)
N
(
Round
N
fractional
reg
=
NOTE: The Round function rounds the number to the nearest
integer.
When in fractional mode, allowed values for Nreg are from 6 to 505
inclusive.
The value to be programmed in the Main or Auxiliary Dividend
Register is given by:
)]
32
N
(
divider
[
Round
dividend
reg
fractional
×
=
where the divider is either 1024 in 10-bit mode or 262144 in
18-bit mode. Therefore, the dividend is a signed binary value
either 10 or 18 bits long.
NOTE: Because of the high fractionality of the CX72302, there is
no practical need for any integer relationship between
the reference frequency and the channel spacing or
desired VCO frequencies.
Sample calculations for two fractional-N applications are provided
in Figure 4.
Integer-N Applications. The desired division ratio for the main or
auxiliary synthesizer is given by:
ref
_
div
main
_
vco
eger
int
F
N
=
where Ninteger is an integer number from 32 to 543 for both the
main and auxiliary synthesizers.
The value to be programmed in the Main or Auxiliary Divider
Register is given by:
32
N
eger
int
reg
=
When in integer mode, allowed values for Nreg are from 0 to 511
for both the main and auxiliary synthesizers.
NOTE: As with all integer-N synthesizers, the minimum step size
is related to the crystal frequency and reference
frequency division ratio.
A sample calculation for an integer-N application is provided in
Figure 5.
Register Loading Order. In applications where the main
synthesizer is in 18-bit mode, the Main Dividend MSB Register
holds the 10 MSBs of the dividend and the Main Dividend LSB
Register holds the 8 LSBs of the dividend. The registers that
control the main synthesizer’s divide ratio are to be loaded in the
following order:
Main Divider Register
Main Dividend LSB Register
Main Dividend MSB Register (at which point the new divide ratio
takes effect)
In applications where the main synthesizer is in 10-bit mode, the
Main Dividend MSB Register holds the 10 bits of the dividend. The
registers that control the main synthesizer’s divide ratio are to be
loaded in the following order:
Main Divider Register
Main Dividend MSB Register (at which point the new divide ratio
takes effect)
For the auxiliary synthesizer, the Auxiliary Dividend Register holds
the 10 bits of the dividend. The registers that control the auxiliary
synthesizer’s divide ratio are to be loaded in the following order:
Auxiliary Divider Register
Auxiliary Dividend Register (at which point the new divide ratio
takes effect)
NOTE: When in integer mode, the new divide ratios take effect
as soon as the Main or Auxiliary Divider Register is
loaded.
Direct Digital Modulation
The high fractionality and small step size of the CX72302 allow
the user to tune to practically any frequency in the VCO’s
operating range. This frequency tuning allows direct digital
modulation by programming the different desired frequencies at
precise instants. Typically, the channel frequency is selected
through the Main Divider and Dividend Register and the
instantaneous frequency offset from the carrier is entered through
the Modulation Data Register.
The Modulation Data Register can be accessed in three ways,
which are defined in the following subsections.
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