參數(shù)資料
型號: CXD2470R
廠商: Sony Corporation
英文描述: Timing Generator for Frame Readout CCD Image Sensor
中文描述: 時序發(fā)生器傳感器讀出CCD圖像幀
文件頁數(shù): 10/38頁
文件大?。?/td> 405K
代理商: CXD2470R
– 10 –
CXD2470R
Serial interface clock output variation characteristics
Normally, the serial interface data is loaded to the CXD2470R at the timing shown in "Serial interface clock
internal loading characteristics (1)" above. However, one exception to this is when the data such as STB is
loaded to the CXD2470R and controlled at the rising edge of SEN. See "Description of Operation".
0.8V
DDd
SEN
Output signal
tpdPULSE
Symbol
tpdPULSE
Definition
Output signal delay, activated by the rising edge of SEN
Min.
Typ.
Max.
100
5
Unit
ns
(Within the recommended operating conditions)
Serial interface clock internal loading characteristics (2)
th1
Enlarged view
0.2V
DDd
ts1
0.2V
DDd
VDI
HDI
VDI
HDI
SEN
0.8V
DDd
Example: During frame mode
Symbol
t
s1
t
h1
Definition
SEN setup time, activated by the falling edge of VDI
SEN hold time, activated by the falling edge of VDI
Min.
Typ.
Max.
0
200
Unit
ns
ns
Be sure to maintain a constantly high SEN logic level near the falling edge of VDI.
(Within the recommended operating conditions)
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