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參數(shù)資料
| 型號： | CXD2498R |
| 廠商： | Sony Corporation |
| 英文描述： | Timing Generator for Frame Readout CCD Image Sensor |
| 中文描述： | 時(shí)序發(fā)生器傳感器讀出CCD圖像幀 |
| 文件頁數(shù)： | 4/51頁 |
| 文件大?。?/td> | 554K |
| 代理商： | CXD2498R |
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4
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CXD2498R
Pin Description
Pin
No.
1
Symbol
I/O
Description
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
V
SS
1
RST
SNCSL
ID/EXP
WEN
SSGSL
V
DD
1
RG
V
SS
2
H1A
V
DD
2
H1B
H2A
V
SS
3
H2B
V
DD
3
V
DD
4
XSHP
XSHD
PBLK
CLPDM
OBCLP
ADCLK
V
SS
4
CKO
CKI
TEST1
TEST2
V
DD
5
MCKO
SSI
—
I
I
O
O
I
—
O
—
O
—
O
O
—
O
—
—
O
O
O
O
O
O
—
O
I
I
I
—
O
I
GND
Internal system reset input.
Normally apply reset during power-on.
High: Normal operation, Low: Reset control
Schmitt trigger input
Control input used to switch sync system.
High: CKI sync, Low: MCKO sync
With pull-down resistor
Vertical direction line identification pulse output/exposure time identification pulse
output.
Switching possible using the serial interface data. (Default: ID)
Memory write timing pulse output.
Internal SSG enable.
High: Internal SSG valid, Low: External sync valid
With pull-down resistor
3.3V power supply. (Power supply for common logic block)
CCD reset gate pulse output.
GND
CCD horizontal register clock output.
3.3V power supply. (Power supply for H block)
CCD horizontal register clock output.
CCD horizontal register clock output.
GND
CCD horizontal register clock output.
3.3V power supply. (Power supply for H block)
3.3V power supply. (Power supply for CDS block)
CCD precharge level sample-and-hold pulse output.
CCD data level sample-and-hold pulse output.
Pulse output for horizontal and vertical blanking period pulse cleaning.
CCD dummy signal clamp pulse output.
CCD optical black signal clamp pulse output.
The horizontal OB pattern can be changed using the serial interface data.
Clock output for analog/digital conversion IC.
Logical phase adjustment possible using the serial interface data.
GND
Inverter output.
Inverter input.
IC test pin 1; normally fixed to GND.
With pull-down resistor
IC test pin 2; normally fixed to GND.
With pull-down resistor
3.3V power supply. (Power supply for common logic block)
System clock output for signal processing IC.
Serial interface data input for internal mode settings.
Schmitt trigger input
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| CXD2500AQ | CD DIGITAL SIGNAL PROCESSOR |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CXD2500AQ | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:CD DIGITAL SIGNAL PROCESSOR |
| CXD2500AQZ | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:CD DIGITAL SIGNAL PROCESSOR |
| CXD2500BQ | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:CD Digital Signal Processor |
| CXD2507AQ | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:CD Digital Signal Processor |
| CXD2508AQ | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:CD Digital Signal Processor |
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