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參數(shù)資料
| 型號： | CXD2510Q |
| 廠商： | Sony Corporation |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | CD Digital Signal Processor |
| 中文描述： | CD數(shù)字信號處理器 |
| 文件頁數(shù)： | 31/48頁 |
| 文件大?。?/td> | 743K |
| 代理商： | CXD2510Q |
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CXD2510Q
§3. Description of Other Functions
§3-1. Channel Clock Regeneration by the Digital PLL Circuit
The channel clock is necessary for demodulating the EFM signal regenerated by the optical system.
Assuming T as the channel clock cycle, the EFM signal is modulated in an integer multiple of T from 3T to
11T. In order to read the information in the EFM signal, this integer value must be read correctly. As a
result, T, that is the channel clock, is necessary.
In an actual player, PLL is necessary to regenerate the channel clock because the fluctuation in the spindle
rotation alters the width of the EFM signal pulses.
The block diagram of this PLL is shown in Fig. 3-1.
The CXD2510Q has a built-in three-stage PLL.
The first-stage PLL regenerates the variable pitch.
LPF and VCO are necessary as external parts.
The minimum variable amount of the pitch is 0.1%. The output of this first-stage PLL is used as a reference
for all clocks within the LSI. Input the XTAO output to the VCKI pin when variable pitch is not used.
The second-stage PLL regenerates a high-frequency clock needed by the third-stage digital PLL.
The third-stage PLL is a digital PLL that regenerates the actual channel clock, and has a ±150kHz (normal
state) or more capture range.
The digital PLL has a secondary loop, and is controlled by the primary loop (phase) and the secondary loop
(frequency). When FLFC = 1, the secondary loop can be turned off .
High-frequency components such as 3T and 4T may contain deviations. In such a case, turning the
secondary loop off yields better playability.
However, in this case the capture range becomes 50kHz.
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