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參數(shù)資料
| 型號(hào)： | CXK77B1841GB |
| 廠商： | Sony Corporation |
| 英文描述： | 4Mb Late Write LVTTL High Speed Synchronous SRAM (256K x 18Bit)(4M位、寫延遲、LVTTL高速同步靜態(tài)RAM (256K x 18位)) |
| 中文描述： | 4Mb的后寫入LVTTL高速同步SRAM（256 × 18位）（4分位，寫延遲，LVTTL高速同步靜態(tài)隨機(jī)存儲(chǔ)器（256 × 18位）） |
| 文件頁數(shù)： | 18/22頁 |
| 文件大?。?/td> | 199K |
| 代理商： | CXK77B1841GB |
256Kx18, Sync LW, LVTTL, rev 4.6
18 / 22
August 12, 1998
SONY
CXK77B1841GB
Test Mode Description
Functional Description
The CXK77B1841 provides a JTAG boundary scan interface using a limited set of IEEE std. 1149.1
functions. The test mode is intended to provide a mechanism for testing the interconnect between master
(processor, controller, etc.), SRAMs, other components and the printed circuit board.
In conformance with a subset of IEEE std. 1149.1, the CXK77B1841 contains a TAP controller, Instruc-
tion register, Boundary scan register and Bypass register.
JTAG Inputs/Outputs are LVTTL compatible only.
Test Access Port (TAP)
4 pins as defined in the Pin Description table are used to perform JTAG functions. The TDI input pin is
used to scan test data serially into one of three registers (Instruction register, Boundary Scan register and
Bypass register). TDO is the output pin used to scan test data serially out. The TDI pin sends the data
into LSB of the selected register and the MSB of the selected register feeds the data to TDO. The TMS
input pin controls the state transition of 16 state TAP controller as specified in IEEE std. 1149.1. Inputs
on TDI and TMS are registered on the rising edge of TCK clock. The output data on TDO is presented
on the falling edge of TCK. TDO driver is in active state only when TAP controller is in Shift-IR state
or in Shift-DR state.
TCK, TMS, TDI must be tied low when JTAG is not used.
TAP Controller
16 state controller is implemented as specified in IEEE std. 1149.1.
The controller enters reset state in one of two ways:
1. Power up.
2. Apply a logic 1 on TMS input pin on 5 consecutive TCK rising edges.
Instruction Register (3 bits)
The JTAG Instruction register consists of a shift register stage and parallel output latch. The register is
3 bits wide and is encoded as follow:
Octal
MSB..........LSB
Instruction
0
0
0
0
Bypass
1
0
0
1
IDCODE. Read device ID
2
0
1
0
Sample-Z. Sample Inputs and tri-state DQs
3
0
1
1
Bypass
4
1
0
0
Sample. Sample Inputs.
5
1
0
1
Private. Manufacturer use only.
6
1
1
0
Bypass
7
1
1
1
Bypass
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| CXK77B3611AGB- | High Speed Bi-CMOS Synchronous Static RAM |
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| CXK77B3611AGB-6 | High Speed Bi-CMOS Synchronous Static RAM |
| CXK77B3611AGB | High Speed 1MBit Bi-CMOS Synchronous Static RAM(高速1M位、Bi-CMOS同步靜態(tài)RAM) |
| CXK77B3640AGB | 4Mb Late Write HSTL High Speed Synchronous SRAM(128K x 36Bit)(4M位、寫延遲、高速邏輯收發(fā)（HSTL）、高速同步靜態(tài)RAM (128K x 36位)) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CXK77B1841GB-5 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x18 Fast Synchronous SRAM |
| CXK77B1841GB-6 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x18 Fast Synchronous SRAM |
| CXK77B3610AGB-5R | 制造商:Sony Batteries 功能描述:77B3610AGB-5R |
| CXK77B3610GB- | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:High Speed Bi-CMOS Synchronous Static RAM |
| CXK77B3610GB-6 | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:High Speed Bi-CMOS Synchronous Static RAM |
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