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參數(shù)資料
| 型號(hào)： | CY2277APVC-12T |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 66.67 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | SSOP-48 |
| 文件頁(yè)數(shù)： | 14/19頁(yè) |
| 文件大小： | 209K |
| 代理商： | CY2277APVC-12T |
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CY2277A
Document #: 38-07332 Rev. *A
Page 4 of 19
Serial Configuration Map
The Serial bits will be read by the clock driver in the following
order:
Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0
.
Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0
Reserved and unused bits should be programmed to “0”.
SMBus Address for the CY2277A is:
Power Management Logic
CPU_STOP
PCI_STOP
PWR_DWN
CPUCLK
PCICLK
PCICLK_F
Other Clocks
Osc.
PLLs
X
0
LOW
Stopped
Off
0
1
LOW
Running
0
1
LOW
33/30 MHz
Running
1
0
1
66/60 MHz
LOW
Running
1
66/60 MHz
33/30 MHz
Running
A6
A5
A4
A3
A2
A1
A0
R/W
1101001
----
Byte 0: Functional and Frequency Select Clock
Register (1 = Enable, 0 = Disable)
Bit
Pin #
Description
Bit 7 --
(Reserved) drive to ‘0’
Bit 6 --
(Reserved) drive to ‘0’ on -1, -1M, -3, -7M, -12,
-12M, -12I
Bit 5 --
(Reserved) drive to ‘0’ on -1, -1M, -3, -7M, -12,
-12M, -12I
Bit 4 --
(Reserved) drive to ‘0’ on -1, -1M, -3, -7M, -12,
-12M, -12I
Bit 3 23
48/24 MHz (Frequency Select) 1 = 48 MHz
(default), 0 = 24 MHz
Bit 2 22
48/24 MHz (Frequency Select) 1 = 48 MHz
(default), 0 = 24 MHz
Bit 1
Bit 0
--
Bit 1
1
0
Bit 0
1 - Three-State (see table below)
0 - N/A
1 - Test Mode (see table below)
0 - Normal Operation
Select Functions
Functional Description
Outputs
CPU
PCI, PCI_F
SDRAM
Ref
IOAPIC
IOCLK
USBCLK
Three-State
Hi-Z
Test Mode
TCLK/2[5]
TCLK/4
TCLK/2
TCLK
TCLK/4
TCLK/2
Note:
5.
TCLK supplied on the XTALIN, PIN 4.
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