參數(shù)資料
型號: CY2277APVC-12T
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: 時鐘產(chǎn)生/分配
英文描述: 66.67 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
封裝: SSOP-48
文件頁數(shù): 5/19頁
文件大?。?/td> 209K
代理商: CY2277APVC-12T
CY2277A
Document #: 38-07332 Rev. *A
Page 13 of 19
Timing Requirement for the SMBus
Parameter
Description
Min.
Max.
Unit
t10
SCLK Clock Frequency
0
100
kHz
t11
Time the bus must be free before a new transmission can start
4.7
s
t12
Hold time start condition. After this period the first clock pulse is generated.
4
s
t13
The LOW period of the clock.
4.7
s
t14
The HIGH period of the clock.
4
s
t15
Setup time for start condition. (Only relevant for a repeated start condition.)
4.7
s
t16
Hold time DATA
for CBUS compatible masters.
for SMBus devices
5
0
s
t17
DATA input set-up time
250
ns
t18
Rise time of both SDATA and SCLK inputs
1
s
t19
Fall time of both SDATA and SCLK inputs
300
ns
t20
Set-up time for stop condition
4.0
s
Switching Waveforms
Duty Cycle Timing
t1A
t1B
CPUCLK Outputs HIGH/LOW Time
OUTPUT
VDD
0V
t1C
t1D
All Outputs Rise/Fall Time
OUTPUT
t2
t3
VDD
0V
t2
t4
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