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參數(shù)資料
| 型號(hào)： | CY2277APVC-12T |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 66.67 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | SSOP-48 |
| 文件頁數(shù)： | 19/19頁 |
| 文件大?。?/td> | 209K |
| 代理商： | CY2277APVC-12T |
CY2277A
Document #: 38-07332 Rev. *A
Page 9 of 19
Switching Characteristics (-1, -3)[9, 10, 11]
Parameter
Output
Description
Test Conditions
Min.
Typ.
Max.
Unit
t1
CPUCLK
SDRAM
USBCLK
IOCLK
REF [0,1]
IOAPIC
Output Duty Cycle[12]
t1 = t1A ÷ t1B
45
50
55
%
t1
PCI
Output Duty Cycle[12]
t1 = t1A ÷ t1B
40
50
55
%
t2
CPUCLK,
IOAPIC
CPU and IOAPIC Clock
Rising and Falling Edge
Rate
Between 0.4V and 2.0V, VDDCPU = 2.5V
Between 0.4V and 2.4V, VDDCPU = 3.3V
CPU clocks at 66.66 MHz
0.75
4.0
V/ns
t2
PCI
PCI Clock Rising and
Falling Edge Rate
Between 0.4V and 2.4V, VDDCPU = 3.3V
0.75
4.0
V/ns
t2
USBCLK,
IOCLK,
REF0
USB, I/O, REF0 Clock
Rising and Falling Edge
Rate
Between 0.4V and 2.4V
0.8
4.0
V/ns
t2
SDRAM
SDRAM Rising and Fall-
ing Edge Rate
Between 0.4V and 2.4V
SDRAM clocks at 66.66 MHz
1.0
4.0
V/ns
t2
REF1
REF1 Rising and Falling
Edge Rate
Between 0.4V and 2.4V
0.5
2.0
V/ns
t3
CPUCLK
CPU Clock Rise Time
Between 0.4V and 2.0V, VDDCPU = 2.5V
Between 0.4V and 2.4V, VDDCPU = 3.3V
0.4
0.5
2.13
2.0
ns
t3
USBCLK,
IOCLK
USB Clock and I/O Clock
Rise Time
Between 0.4V and 2.4V
2.5
ns
t4
CPUCLK
CPU Clock Fall Time
Between 2.0V and 0.4V, VDDCPU = 2.5V
Between 2.4V and 0.4V, VDDCPU = 3.3V
0.4
0.5
2.13
2.0
ns
t4
USBCLK,
IOCLK
USB Clock and I/O Clock
Fall Time
Between 2.4V and 0.4V
2.5
ns
t5
CPUCLK
CPU-CPU Clock Skew
Measured at 1.25V, VDDCPU = 2.5V
100
400
ps
t6
CPUCLK,
PCICLK
CPU-PCI Clock Skew
(-1, -3)
Measured at 1.25V for 2.5V clocks, and
at 1.5V for 3.3V clocks
1.0
2.0
6.0
ns
t7
CPUCLK,
SDRAM
CPU-SDRAM Clock
Skew
Measured at 1.25V for 2.5V clocks, and
at 1.5V for 3.3V clocks, VDDCPU = 2.5V
775
ps
t8
CPUCLK
Cycle-Cycle Clock Jitter
Measured at 1.25V for 2.5V clocks and
at 1.5V for 3.3V clocks
450
ps
t8
SDRAM
Cycle-Cycle Clock Jitter
Measured at 1.5V for 3.3V clocks
650
ps
t8
PCICLK
Cycle-Cycle Clock Jitter
Measured at 1.5V
500
ps
t8
USBCLK,
IOCLK
Cycle-Cycle Clock Jitter
Measured at 1.5V
1.3
ns
t9
CPUCLK,
PCICLK,
SDRAM
Power-up Time
CPU, PCI, and SDRAM clock stabiliza-
tion from power-up
3
ms
t10
CPU, PCI,
SDRAM
Frequency Slew Rate
Rate of change of frequency
2
MHz/
ms
Notes:
9.
All parameters specified with loaded outputs.
10. Over the operating range unless otherwise specified.
11.
Parameters specified with: VDDCPU = 2.5V, VDDQ2 = 2.5V, VDDQ3 = 3.3V.
12. Duty cycle is measured at 1.5V when VDD = 3.3V. When VDDCPU = 2.5V, CPUCLK duty cycle is measured at 1.25V.
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