參數(shù)資料
型號： CY28341-2
廠商： Cypress Semiconductor Corp.
英文描述： Universal Clock Chip for VIA P4M/KT/KM400 DDR Systems
中文描述： 通用時鐘芯片的威盛P4M/KT/KM400的DDR系統(tǒng)
文件頁數(shù)： 17/19頁
文件大?。?/td> 174K
代理商： CY28341-2
CY28341-2
Document #: 38-07471 Rev. *B
Page 17 of 19
T
SKEW
T
CCJ
PCI
T
DC
T
PERIOD
T
HIGH
T
LOW
T
R
/ T
F
T
SKEW
T
CCJ
48 MHz
T
DC
T
PERIOD
T
R
/ T
F
T
CCJ
24 MHz
T
DC
T
PERIOD
T
R
/ T
F
T
CCJ
REF
T
DC
T
PERIOD
Any AGP to Any AGP Clock Skew
AGP(0:2) Cycle-to-Cycle Jitter
250
500
250
500
250
500
ps 8,14
ps 8,9,14
PCI(_F,1:6) Duty Cycle
PCI(_F,1:6) Period
PCI(_F,1:6) High Time
PCI(_F,1:6) Low Time
PCI(_F,1:6) Rise and Fall Times
Any PCI to Any PCI Clock Skew
PCI(_F,1:6) Cycle-to-Cycle Jitter
45
30.0
12.0
12.0
0.5
55
45
30.0
12.0
12.0
0.5
55
45
30.0
12.0
12.0
0.5
55
% 7,8,9
ns 7,8,9
ns 8,21
ns 8,10
ns 8,13
ps 8,14
ps 8,9,14
2.5
500
500
2.5
500
500
2.5
500
500
48-MHz Duty Cycle
48-MHz Period
48-MHz Rise and Fall Times
48-MHz Cycle-to-Cycle Jitter
45
55
45
55
45
55
% 7,8,9
20.8299 20.8333 20.8299 20.8333 20.8299 20.8333 ns 7,8,9
1.0
4.0
1.0
4.0
500
500
1.0
4.0
500
ns 8,13
ps 8,9,14
24-MHz Duty Cycle
24-MHz Period
24-MHz Rise and Fall Times
24-MHz Cycle-to-Cycle Jitter
45
55
45
55
45
55
% 7,8,9
ns 7,8,9
ns 8,13
ps 8,9,14
41.660
1.0
41.667
4.0
500
41.660 41.667 41.660 41.667
1.0
4.0
500
1.0
4.0
500
REF Duty Cycle
REF Period
45
55
71.0
45
55
71.0
45
55
71.0
% 7,8,9
ns 7,8,9
69.841
3
1.0
69.841
3
1.0
69.841
3
1.0
T
R
/ T
F
T
CCJ
DDR
V
X
REF Rise and Fall Times
REF Cycle-to-Cycle Jitter
4.0
1000
4.0
1000
4.0
1000
ns 8,13
ps 8,9,14
Crossing Point Voltage of DDRT/C
0.5*V
D
DD
–0.2
0.7
0.5*V
DDD
+0.2
VDDD +
0.6
55
10.2
3
0.5*V
D
DD
–0.2
0.7
0.5*V
D
DD
+0.2
VDDD
+ 0.6
55
15.3
3
0.5*V
D
DD
–0.2
0.7
0.5*V
D
DD
+0.2
VDDD
+ 0.6
55
10.2
3
V
15
V
D
Differential Voltage Swing
V
23
T
DC
T
PERIOD
T
R
/ T
F
DDRT/C(0:5) Duty Cycle
DDRT/C(0:5) Period
DDRT/C(0:5) Rise/Fall Slew Rate
45
9.85
1
45
45
9.85
1
% 11
ns 11
V/n
s
ps 8,14,11
ps 8,14,11
ps 8,14,11
ns 8,9
ps 8,9
ms 22
14.85
1
13
T
SKEW
T
CCJ
T
HPJ
T
DELAY
T
SKEW
T
STABLE
DDRT/C to any DDRT/C Clock Skew
DDRT/C(0:5) Cycle-to-Cycle Jitter
DDRT/C(0:5) Half-period Jitter
BUF_IN to Any DDRT/C Delay
FBOUT to Any DDRT/C Skew
All-Clock Stabilization from Power-up
100
±75
±100
4
100
3
100
±75
±100
4
100
3
100
±75
±100
4
100
3
1
1
1
AC Parameters
(continued)
Parameter
Description
100 MHz
Min.
133 MHz
Min.
200 MHz
Min.
Unit
Notes
Max.
Max
Max.
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相關代理商/技術參數(shù)
參數(shù)描述
CY28341-2_05 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Universal Clock Chip for VIA⑩P4M/KT/KM400 DDR Systems
CY28341-3 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Universal Clock Chip for VIA⑩P4M/KT/KM400A DDR Systems
CY28341OC 制造商:Rochester Electronics LLC 功能描述:FTG FOR VIA P4 CHIPSET - Bulk
CY28341OC-2 制造商:Rochester Electronics LLC 功能描述:- Bulk
CY28341OC-2T 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Universal Clock Chip for VIA⑩P4M/KT/KM400 DDR Systems
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