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參數(shù)資料
| 型號(hào)： | CY28341-2 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Universal Clock Chip for VIA P4M/KT/KM400 DDR Systems |
| 中文描述： | 通用時(shí)鐘芯片的威盛P4M/KT/KM400的DDR系統(tǒng) |
| 文件頁(yè)數(shù)： | 5/19頁(yè) |
| 文件大?。?/td> | 174K |
| 代理商： | CY28341-2 |
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CY28341-2
Document #: 38-07471 Rev. *B
Page 5 of 19
Serial Control Registers
Table 4. Byte Read and Byte Write Protocol
Byte Write Protocol
Description
Byte Read Protocol
Bit
1
2:8
9
10
11:18
Bit
1
2:8
9
10
11:18
Description
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8-bit ‘1xxxxxxx’ stands for byte
operationbit[6:0] of the command code repre-
sents the offset of the byte to be accessed
Acknowledge from slave
Byte Count – 8 bits
Acknowledge from slave
stop
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8-bit ‘1xxxxxxx’ stands for byte
operationbit[6:0] of the command code repre-
sents the offset of the byte to be accessed
Acknowledge from slave
Repeat start
Slave address – 7 bits
Read
Acknowledge from slave
Data byte from slave – 8 bits
Not Acknowledge
stop
19
19
20
20:27
28
29
21:27
28
29
30:37
38
39
Byte 0: Frequency Select Register
Bit
7
6
5
4
3
@Pup
0
H/W Setting
H/W Setting
H/W Setting
0
Pin#
Name
Reserved
FS2
FS1
FS0
Description
Reserved
For Selecting Frequencies in
Frequency Selection Table
on page 1
For Selecting Frequencies in
Frequency Selection Table
on page 1
For Selecting Frequencies in
Frequency Selection Table
on page 1
If this bit is programmed to “1”, it enables WRITE to bits (6:4,1) for
selecting the frequency via software (SMBus)
If this bit is programmed to a “0” it enable only READ of bits (6:4,1),
which reflect the hardware setting of FS(0:3).
SELSDR_DDR Only for reading the hardware setting of the SDRAM interface mode,
status of SELSDR_DDR# strapping.
FS3
For Selecting frequencies in
Frequency Selection Table
on page 1
SELP4_K7
Only for reading the hardware setting of the CPU interface mode,
status of SELP4_K7# strapping.
21
10
1
2
H/W Setting
11
1
0
H/W Setting
H/W Setting
20
7
Byte 1: CPU Clocks Register
Bit
7
6
5
4
3
@Pup
0
1
1
1
1
Pin#
Name
Description
MODE
SSCG
SST1
SST0
0 = Down Spread. 1 = Center Spread.
See Table 9
on page 9
1 = Enable (default). 0 = Disable
Select spread bandwidth.
See Table 9
on page 9
Select spread bandwidth.
See Table 9
on page 9
1 = output enabled (running). 0 = output disabled asynchronously in a low
state.
1 = output enabled (running). 0 = output disable.
48,49 CPUCS_T, CPUCS_C
2
1
53,52 CPUT/CPUOD_T
CPUC/CPUOD_C
53,52 CPUT/C
1
1
In K7 mode, this bit is ignored.In P4 mode, 0 = when PD# asserted LOW,
CPUT stops in a high state, CPUC stops in a low state. In P4 mode, 1 = when
PD# asserted LOW, CPUT and CPUC stop in High-Z.
Only for reading the hardware setting of the Pin11 MULT0 value.
0
1
11
MULT0
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY28341-2_05 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Universal Clock Chip for VIA⑩P4M/KT/KM400 DDR Systems |
| CY28341-3 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Universal Clock Chip for VIA⑩P4M/KT/KM400A DDR Systems |
| CY28341OC | 制造商:Rochester Electronics LLC 功能描述:FTG FOR VIA P4 CHIPSET - Bulk |
| CY28341OC-2 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY28341OC-2T | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Universal Clock Chip for VIA⑩P4M/KT/KM400 DDR Systems |
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