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參數(shù)資料
| 型號(hào)： | CY2SSTV850ZIT |
| 廠商： | Silicon Laboratories Inc |
| 文件頁(yè)數(shù)： | 3/9頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK DIFFDRV PLL DDR 48TSSOP |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 類型： | * |
| PLL： | 帶旁路 |
| 輸入： | 時(shí)鐘 |
| 輸出： | 時(shí)鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:10 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 170MHz |
| 除法器/乘法器： | 無(wú)/無(wú) |
| 電源電壓： | 2.375 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | * |
| 封裝/外殼： | * |
| 供應(yīng)商設(shè)備封裝： | * |
| 包裝： | * |
CY2SSTV850
......................... Document #: 38-07457 Rev. *A Page 3 of 9
Power Management
The
individual
output
enable/disable
control
of
the
CY2SSTV850 allows the user to implement unique power
management
schemes
into
the
design.
Outputs
are
three-stated when disabled through the two-line interface as
individual bits are set low in Byte 0 and Byte 1 registers. The
feedback output pair (FBOUTT, FBOUTC) cannot be disabled
via two-line serial bus. The enabling and disabling of individual
outputs is done in such a manner as to eliminate the possibility
of partial “runt” clocks.
Zero-delay Buffer
When used as a zero-delay buffer the CY2SSTV850 will likely
be in a nested clock tree application. For these applications
the CY2SSTV850 offers a differential clock input pair as a PLL
reference. The CY2SSTV850 then can lock onto the reference
and translate with near zero delay to low-skew outputs. For
normal operation, the external feedback input, FBINT, is
connected to the feedback output, FBOUTT. By connecting
the feedback output to the feedback input the propagation
delay through the device is eliminated. The PLL works to align
the output edge with the input reference edge thus producing
a near zero delay. The reference frequency affects the static
phase offset of the PLL and thus the relative delay between
the inputs and outputs.
When AVDD is strapped low, the PLL is turned off and
bypassed for test purposes.
Serial Control Registers
Following the acknowledge of the Address Byte, two additional
bytes must be sent:
“Command Code” byte, and “Byte Count” byte.
2 Line Serial Interface
Note:
3. Each output pair can be three-stated via the two-line serial interface.
Function Table
Inputs
Outputs
PLL
AVDD
CLKINT
CLKINC
YT(0:9)[3]
YC(0:9)[3]
FBOUTT
FBOUTC
GND
L
H
L
H
L
H
BYPASSED/OFF
GND
H
L
H
L
H
L
BYPASSED/OFF
2.5V
L
H
L
H
L
H
On
2.5V
H
L
H
L
H
L
On
Nom
Design
Nom
Design
2.5V
<20 MHz
<30 MHZ <20 MHz <30 MHz
Hi-Z
Off
Byte0: Output Register (1 = Enable, 0 = Disable)
Bit
@Pup
Pin#
Description
71
3, 2
YT0, YC0
61
5, 6
YT1, YC1
51
10, 9
YT2, YC2
4
1
20, 19
YT3, YC3
3
1
22, 23
YT4, YC4
2
1
46, 47
YT5, YC5
1
44, 43
YT6, YC6
0
1
39, 40
YT7, YC7
Byte1: Output Register (1 = Enable, 0 = Disable)
Bit
@Pup
Pin#
Description
7
1
29, 30
YT8, YC8
6
1
27, 26
YT9, YC9
50
Reserved
40
Reserved
30
Reserved
20
Reserved
10
Reserved
00
Reserved
2-Line Serial Interface Slave Address
A7
A6
A5
A4
A3
A2
A1
R/W
1
0100
1
0
Writing to the device is accomplished by sequentially sending the device address D2H, the dummy bytes (command code and
the number of bytes), and the data bytes. This sequence is illustrated in the following tables.
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