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參數(shù)資料
| 型號： | CY2SSTV850ZIT |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 6/9頁 |
| 文件大小： | 0K |
| 描述： | IC CLOCK DIFFDRV PLL DDR 48TSSOP |
| 標準包裝： | 2,000 |
| 類型： | * |
| PLL： | 帶旁路 |
| 輸入： | 時鐘 |
| 輸出： | 時鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:10 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 170MHz |
| 除法器/乘法器： | 無/無 |
| 電源電壓： | 2.375 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | * |
| 封裝/外殼： | * |
| 供應商設(shè)備封裝： | * |
| 包裝： | * |
CY2SSTV850
......................... Document #: 38-07457 Rev. *A Page 6 of 9
Note:
11. Parameters are guaranteed by design and characterization. Not 100% tested in production.
12. PLL is capable of meeting the specified parameters while supporting SSC synthesizers with modulation frequency between 30 kHz and 33.3 kHz with a down
spread of –0.5%.
13. While the pulse skew is almost constant over frequency, the duty cycle error increases at higher frequencies. This is due to the formula: duty cycle = tWH/tC, where
the cycle time (tC) decreases as the frequency goes up.
14. Refers to transition of non-inverting output.
15. Period Jitter and Half-Period Jitter specifications are separate specifications that must be met independently of each other.
16. All differential input and output terminals are terminated with 120
/16 pF as shown in Figure 6.
17. DUT refers to Device Under Test.
Parameter
Description
Conditions
Min.
Typ.
Max.
Unit
fCLK
Operating Clock Frequency
AVDD, VDD = 2.5V ± 0.2V
60
170
MHz
tDC
Input Clock Duty Cycle[13]
40
60
%
tlock
Maximum PLL lock Time
100
s
tR/tF
Output Clocks Slew Rate
20% to 80% of VOD
1
2
V/ns
tpZL, tpZH
Output Enable Time[14]
(all outputs)
3
ns
tpLZ, tpHZ
Output Disable Time[14]
(all outputs)
3
ns
tCCJ
Cycle to Cycle Jitter
f > 66 MHz
–100
100
ps
tjit(h-per)
Half-period jitter [15]
f > 66 MHz
–100
100
ps
tPLH
Low-to-High Propagation Delay,
CLKINT to YT[0:9]
1.5
3.5
6ns
tPHL
High-to-Low Propagation Delay,
CLKINT to YT[0:9]
1.5
3.5
6ns
tSK(0)
Any Output to Any Output Skew[16]
100
ps
tPHASE
Phase Error[16]
–150
150
ps
tJITT(PHASE)
Phase Error Jitter
f > 66 MHz
–50
50
ps
td(0)
Dynamic Phase Offset
CLKIN pins to FBIN pins at the
DUT[17]
30
140
ps
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