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參數(shù)資料
| 型號： | CY2SSTV850ZIT |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 5/9頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK DIFFDRV PLL DDR 48TSSOP |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 類型： | * |
| PLL： | 帶旁路 |
| 輸入： | 時鐘 |
| 輸出： | 時鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:10 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 170MHz |
| 除法器/乘法器： | 無/無 |
| 電源電壓： | 2.375 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | * |
| 封裝/外殼： | * |
| 供應(yīng)商設(shè)備封裝： | * |
| 包裝： | * |
CY2SSTV850
......................... Document #: 38-07457 Rev. *A Page 5 of 9
Maximum Ratings[4]
Input Voltage Relative to VSS:...............................VSS – 0.3V
Input Voltage Relative to VDDQ or AVDD: ............. VDD + 0.3V
Storage Temperature: ................................. –65
C to +150C
Operating Temperature:.................................... 0
C to +70C
Maximum Power Supply: ................................................ 3.5V
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric fields; however,
precautions should be taken to avoid application of any
voltage higher than the maximum rated voltages to this circuit.
For proper operation, Vin and Vout should be constrained to the
range:
VSS < (Vin or Vout) < VDD
Unused inputs must always be tied to an appropriate logic
voltage level (either VSS or VDD).
Notes:
4. Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
5. Unused inputs must be held HIGH or LOW to prevent them from floating.
6. Differential input signal voltage specifies the differential voltage |VTR – VCP| required for switching, where VTR is the true input level and VCP is the complementary
input level.
7. Differential cross-point input voltage is expected to track VDDQ and is the voltage at which the differential signals must be crossing.
8. For load conditions see Figure 6.
9. The value of VOC is expected to be |VTR + VCP|/2. In case of each clock directly terminated by a 120 resistor. See Figure 6.
10. All outputs switching loaded with 16 pF in 60
environment. See Figure 6.
Parameter
Description
Conditions
Min.
Typ.
Max.
Unit
VIL
Input Low Voltage
SDATA, SCLK
1.0
V
VIH
Input High Voltage
2.2
V
VID
Differential Input
Voltage[6]
CLKINT, FBINT
0.35
VDDQ + 0.6
V
VIX
Differential Input
Crossing Voltage[7]
CLKTIN, FBINT
(VDDQ/2) –
0.2
VDDQ/2
(VDDQ/2) + 0.2
V
IIN
Input Current
VIN = 0V or VIN = VDDQ, CLKINT,
FBINT
–10
10
A
IOL
Output Low Current
VDDQ = 2.375V, VOUT = 1.2V
26
35
mA
IOH
Output High Current
VDDQ = 2.375V, VOUT = 1V
–18
–32
mA
VOL
Output Low Voltage
VDDQ = 2.375V, IOL = 12 mA
0.6
V
VOH
Output High Voltage
VDDQ = 2.375V, IOH = –12 mA
1.7
V
VOUT
Output Voltage Swing[8]
1.1
VDDQ-0.4
V
VOC
Output Crossing
Voltage[9]
(VDDQ/2) –
0.2
VDDQ/2
(VDDQ/2) + 0.2
V
IOZ
High-Impedance Output
Current
VO = GND or VO = VDDQ
–10
10
A
IDDQ
Dynamic Supply
Current[10]
All VDDQ and VDDI,
FO = 170 MHz
235
300
mA
IDD
PLL Supply Current
AVDD only
9
12
mA
Cin
Input Pin Capacitance
2.5
3
3.5
pF
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