參數(shù)資料
型號(hào)： CY38050V256-125BBI
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： PLD
英文描述： LOADABLE PLD, 10 ns, PBGA256
封裝： 17 X 17 MM, FBGA-256
文件頁(yè)數(shù)： 4/45頁(yè)
文件大小： 720K
代理商： CY38050V256-125BBI
Quantum38K ISR
CPLD Family
Document #: 38-03043 Rev. *G
Page 12 of 45
Development Software Support
Warp
Warp is a state-of-the-art design environment for designing
with Cypress programmable logic. Warp utilizes a subset of
IEEE 1076/1164 VHDL and IEEE 1364 as the Hardware
Description Language (HDL) for design entry. Warp accepts
VHDL or Verilog input, synthesizes and optimizes the entered
design, and outputs a configuration bitstream for the desired
Quantum38K device. For simulation, Warp provides a
graphical waveform simulator as well as VHDL and Verilog
Timing Models.
VHDL and Verilog are open, powerful, non-proprietary
Hardware Description Languages (HDLs) that are standards
for behavioral design entry and simulation. HDL allows
designers to learn a single language that is useful for all facets
of the design process.
Figure 9. JTAG Interface
Instruction Register
Boundary Scan
idcode
Usercode
ISR Prog.
Bypass Reg.
Data Registers
JTAG
TAP
CONTROLLER
TDO
TDI
TMS
TCLK
相關(guān)PDF資料
PDF描述
CY38050V484-125BBC LOADABLE PLD, 10 ns, PBGA484
CY38050V484-125BBI LOADABLE PLD, 10 ns, PBGA484
CY39030Z144-222BBC LOADABLE PLD, 7 ns, PBGA144
CY39030Z144-83BBC LOADABLE PLD, 15 ns, PBGA144
CY39030Z144-83BBI LOADABLE PLD, 15 ns, PBGA144
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY38100V208-125NTI 制造商:Cypress Semiconductor 功能描述:CPLD QUANTUM38K 144K GATES 1536 MCRCLLS IND 0.18UM 2.5V/3.3V - Bulk
CY3858-000 制造商:TE Connectivity 功能描述:2524F0524-1L/9-9-L016 - Cable Rools/Shrink Tubing
CY39 制造商:PLETRONICS 制造商全稱:Pletronics, Inc. 功能描述:Crystals
CY3900I 功能描述:開(kāi)發(fā)軟件 ISR Programming Kit RoHS:否 制造商:Atollic Inc. 產(chǎn)品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors
CY3900I_05 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Delta39K⑩⁄Ultra37000⑩ ISR⑩ Programming Kits
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