參數(shù)資料
型號: CY38050V484-125BBC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: PLD
英文描述: LOADABLE PLD, 10 ns, PBGA484
封裝: 1 MM PITCH, FBGA-484
文件頁數(shù): 23/45頁
文件大?。?/td> 720K
代理商: CY38050V484-125BBC
Quantum38K ISR
CPLD Family
Document #: 38-03043 Rev. *G
Page 3 of 45
Figure 1. Quantum38K100 Block Diagram (3 Rows x 4 Columns) with I/O Bank Structure
4
GCLK[3:0]
4
Channel
RAM
4
GCLK[3:0]
4
GCLK[3:0]
4
GCLK[3:0]
GCTL[3:0]
I/O Bank 6
I/O Bank 7
I/O Bank 3
I/O Bank 2
I/
O
B
a
n
k
4
I/O
Ba
n
k
5
I/O
Ba
n
k
1
I/O
Ba
n
k
0
LB 4
LB 3
LB 0
LB 5
LB 6
LB 7
LB 2
LB 1
PIM
Channel
RAM
Channel
RAM
Channel
RAM
Channel
RAM
Channel
RAM
Channel
RAM
Channel
RAM
Channel
RAM
Channel
RAM
Channel
RAM
Channel
RAM
LB 4
LB 3
LB 0
LB 5
LB 6
LB 7
LB 2
LB 1
PIM
LB 4
LB 3
LB 0
LB 5
LB 6
LB 7
LB 2
LB 1
PIM
LB 4
LB 3
LB 0
LB 5
LB 6
LB 7
LB 2
LB 1
PIM
LB 4
LB 3
LB 0
LB 5
LB 6
LB 7
LB 2
LB 1
PIM
LB 4
LB 3
LB 0
LB 5
LB 6
LB 7
LB 2
LB 1
PIM
LB 4
LB 3
LB 0
LB 5
LB 6
LB 7
LB 2
LB 1
PIM
LB 4
LB 3
LB 0
LB 5
LB 6
LB 7
LB 2
LB 1
PIM
LB 4
LB 3
LB 0
LB 5
LB 6
LB 7
LB 2
LB 1
PIM
LB 4
LB 3
LB 0
LB 5
LB 6
LB 7
LB 2
LB 1
PIM
LB 4
LB 3
LB 0
LB 5
LB 6
LB 7
LB 2
LB 1
PIM
LB 4
LB 3
LB 0
LB 5
LB 6
LB 7
LB 2
LB 1
PIM
相關(guān)PDF資料
PDF描述
CY38050V484-125BBI LOADABLE PLD, 10 ns, PBGA484
CY39030Z144-222BBC LOADABLE PLD, 7 ns, PBGA144
CY39030Z144-83BBC LOADABLE PLD, 15 ns, PBGA144
CY39030Z144-83BBI LOADABLE PLD, 15 ns, PBGA144
CY39030Z208-222NC LOADABLE PLD, 7 ns, PQFP208
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY38100V208-125NTI 制造商:Cypress Semiconductor 功能描述:CPLD QUANTUM38K 144K GATES 1536 MCRCLLS IND 0.18UM 2.5V/3.3V - Bulk
CY3858-000 制造商:TE Connectivity 功能描述:2524F0524-1L/9-9-L016 - Cable Rools/Shrink Tubing
CY39 制造商:PLETRONICS 制造商全稱:Pletronics, Inc. 功能描述:Crystals
CY3900I 功能描述:開發(fā)軟件 ISR Programming Kit RoHS:否 制造商:Atollic Inc. 產(chǎn)品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors
CY3900I_05 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Delta39K⑩⁄Ultra37000⑩ ISR⑩ Programming Kits