參數(shù)資料
型號(hào)： CY38050V484-125BBC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： PLD
英文描述： LOADABLE PLD, 10 ns, PBGA484
封裝： 1 MM PITCH, FBGA-484
文件頁(yè)數(shù)： 7/45頁(yè)
文件大?。?/td> 720K
代理商： CY38050V484-125BBC
Quantum38K ISR
CPLD Family
Document #: 38-03043 Rev. *G
Page 15 of 45
Switching Characteristics—Parameter Descriptions Over the Operating Range [9]
Parameter
Description
Combinatorial Mode Parameters
tPD
Delay from any pin input, through any cluster on the channel associated with that pin input, to any pin output
on the horizontal or vertical channel associated with that cluster
tEA
Global control to output enable
tER
Global control to output disable
tPRR
Asynchronous macrocell RESET or PRESET recovery time from any pin input on the horizontal or vertical
channel associated with the cluster the macrocell is in
tPRO
Asynchronous macrocell RESET or PRESET from any pin input on the horizontal or vertical channel
associated with the cluster that the macrocell is in to any pin output on those same channels
tPRW
Asynchronous macrocell RESET or PRESET minimum pulse width, from any pin input to a macrocell in the
farthest cluster on the horizontal or vertical channel the pin is associated with
Synchronous Clocking Parameters
tMCS
Set-up time of any input pin to a macrocell in any cluster on the channel associated with that input pin,
relative to a global clock
tMCH
Hold time of any input pin to a macrocell in any cluster on the channel associated with that input pin, relative
to a global clock
tMCCO
Global clock to output of any macrocell to any output pin on the horizontal or vertical channel associated
with the cluster that macrocell is in
tIOS
Set-up time of any input pin to the I/O cell register associated with that pin, relative to a global clock
tIOH
Hold time of any input pin to the I/O cell register associated with that pin, relative to a global clock
tIOCO
Clock to output of an I/O cell register to the output pin associated with that register
tSCS
Macrocell clock to macrocell clock through array logic within the same cluster
tSCS2
Macrocell clock to macrocell clock through array logic in different clusters on the same channel
tICS
I/O register clock to any macrocell clock in a cluster on the channel the I/O register is associated with
tOCS
Macrocell clock to any I/O register clock on the horizontal or vertical channel associated with the cluster
that the macrocell is in
tCHZ
Clock to output disable (high-impedance)
tCLZ
Clock to output enable (low-impedance)
fMAX
Maximum frequency with internal feedback—within the same cluster
fMAX2
Maximum frequency with internal feedback—within different clusters at the opposite ends of a horizontal or
vertical channel
Product Term Clock
tMCSPT
Set-up time for macrocell used as input register, from input to product term clock
tMCHPT
Hold time of macrocell used as an input register
tMCCOPT
Product term clock to output delay from input pin
tSCS2PT
Register to register delay through array logic in different clusters on the same channel using a product term
clock
Channel Interconnect Parameters
tCHSW
Adder for a signal to switch from a horizontal to vertical channel and vice-versa
tCL2CL
Cluster to Cluster delay adder (through channels and channel PIM)
Miscellaneous Delays
tCPLD
Delay from the input of a cluster PIM, through a macrocell in the cluster, back to a cluster PIM input. This
parameter can be added to the tPD and tSCS parameters for each extra pass through the AND/OR array
required by a given signal path
tMCCD
Adder for carry chain logic per macrocell
tIOD
Delay from the input of the output buffer to the I/O pin
Note:
9.
Add tCHSW to signals making a horizontal to vertical channel switch or vice-versa.
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