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參數(shù)資料
| 型號： | CY38050V484-83BBC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | PLD |
| 英文描述： | LOADABLE PLD, 15 ns, PBGA484 |
| 封裝： | 1 MM PITCH, FBGA-484 |
| 文件頁數(shù)： | 2/45頁 |
| 文件大小： | 720K |
| 代理商： | CY38050V484-83BBC |
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Quantum38K ISR
CPLD Family
Document #: 38-03043 Rev. *G
Page 10 of 45
The I/O cells do not provide bias voltage support. External
resistors can be used to achieve this per section 3.1.3.1 of
the CompactPCI Hot Swap specification R2.0.
A simple board-level solution is provided in the application
note titled “Hot-Swapping Delta39K and Quantum38K
CPLDs.”
Family, Package, and Density Migration in Quantum38K
CPLDs
The
Quantum38K
CPLDs
combine
dense
logic
with
embedded communications memory. Further design flexibility
is added by the easy migration options available between
different packages, densities and even between Quantum38K
and Delta39K CPLD families.
By making each package offering of Quantum38K CPLD
pin-to-pin compatible with packages of Delta39K CPLD, a
seamless
migration path
is
offered to the users of
Quantum38K CPLDs as their design needs grow. Delta39K
CPLDs offer following enhancements:
— More embedded memory
— Spread Aware PLL
— High-speed I/Os (GTL+, SSTL+, HSTL etc.)
— Higher density devices (up to 200K or 3072 macrocells)
— Higher speed devices (up to 233 MHz)
— Dedicated FIFOs with built-in flag logic
— 1.8V operation
— Self-boot (one chip) solution eliminates need of a boot
EEPROM.
For details on Delta39K CPLD family refer to the data sheet
titled Delta39K ISR CPLD family.
This migration flexibility makes changes or additions to
designs simple even after PCB layout. It also provides the
ability for experimental designs to be used on production
PCBs. Please refer to the application note titled “Family,
Package,
and
Density
Migration
in
Delta39K
and
Quantum38K CPLDs”.
Timing Model
One important feature of the Quantum38K family is the
simplicity
of
its
timing.
All
combinatorial
and
regis-
tered/synchronous delays are worst case and system perfor-
mance is static (as shown in the AC specs section) as long as
data is routed through the same horizontal and vertical
channels. Figure 8 illustrates the true timing model for the
38K100 devices. For synchronous clocking of macrocells, a
delay is incurred from macrocell clock to macrocell clock of
separate Logic Blocks within the same cluster, as well as
separate Logic Blocks within different clusters. This is respec-
tively shown as tSCS and tSCS2 in Figure 8. For combinatorial
paths, any input to any output (from corner to corner on the
device), incurs a worst-case delay in the 38K100 regardless of
the amount of logic or which horizontal and vertical channels
are used. This is the tPD shown in Figure 8. For synchronous
systems, the input set-up time to the output macrocell register
and the clock to output time are shown as the parameters tMCS
and tMCCO shown in the Figure 8. These measurements are
for any output and synchronous clock, regardless of the logic
placement.
The Quantum38K features:
no dedicated vs. I/O pin delays
no penalty for using 0–16 product terms
no added delay for steering product terms
no added delay for sharing product terms
no output bypass delays.
The simple timing model of the Quantum38K family eliminates
unexpected performance penalties.
IEEE 1149.1-compliant JTAG Operation
The Quantum38K family has an IEEE 1149.1 JTAG interface
for both Boundary Scan and ISR operations.
Four dedicated pins are reserved on each device for use by
the Test Access Port (TAP).
Boundary Scan
The Quantum38K family supports Bypass, Sample/Preload,
Extest, Intest, Idcode and Usercode boundary scan instruc-
tions. The JTAG interface is shown in Figure 9.
In-System Reprogramming (ISR)
In-System Reprogramming is the combination of the capability
to program or reprogram a device on-board, and the ability to
support design changes without changing the system timing
or device pinout. This combination means design changes
during debug or field upgrades do not cause board respins.
The Quantum38K family implements ISR by providing a IEEE
std 1149.1 JTAG compliant interface for on-board configu-
ration. Robust routing resources offer pinout flexibility and a
simple timing model provides consistent system performance.
Configuration
Quantum38K is a SRAM based volatile device family that uses
Cypress’s CY3LV series of CPLD boot EEPROM to store
configuration data. Please refer to the data sheet titled “CPLD
Boot EEPROM” and the application note titled “Configuring
Delta39K/Quantum38K” for more details on configuration and
interface set-up between Quantum38K and CPLD boot
PROM.
These
documents
can
be
found
at
http://www.cypress.com.
For Quantum38K design, configuration is defined as the
loading of a user’s design into the volatile Quantum38K die.
Programming, on the other hand, is the loading of a user’s
design into the serial boot PROM.
Device configuration can begin in two ways. It can be initiated
by toggling the Reconfig pin from LOW to HIGH, or by issuing
the appropriate IEEE std 1149.1 JTAG instruction to the
Quantum38K device via the JTAG interface. There are two
IEEE std 1149.1 JTAG instructions that initiate configuration of
the Quantum38K. The Self Config instruction causes the
Quantum38K to (re)configure with data stored in the serial
boot PROM. The Load Config instruction causes the
Quantum38K to (re)configure according to data provided by
other sources such as a PC, automatic test equipment (ATE),
or an embedded micro-controller/processor via the JTAG
interface.
There are two configuration options available for issuing the
IEEE std 1149.1 JTAG instructions to the Quantum38K. The
first method is to use a PC with the C3 ISR programming cable
and software. With this method, the ISR pins of the
Quantum38K devices in the system are routed to a connector
at the edge of the printed circuit board. The C3 ISR
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY38100V208-125NTI | 制造商:Cypress Semiconductor 功能描述:CPLD QUANTUM38K 144K GATES 1536 MCRCLLS IND 0.18UM 2.5V/3.3V - Bulk |
| CY3858-000 | 制造商:TE Connectivity 功能描述:2524F0524-1L/9-9-L016 - Cable Rools/Shrink Tubing |
| CY39 | 制造商:PLETRONICS 制造商全稱:Pletronics, Inc. 功能描述:Crystals |
| CY3900I | 功能描述:開發(fā)軟件 ISR Programming Kit RoHS:否 制造商:Atollic Inc. 產(chǎn)品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| CY3900I_05 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Delta39K⑩⁄Ultra37000⑩ ISR⑩ Programming Kits |
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