參數(shù)資料
型號： CY39200V676-167MBC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： PLD
英文描述： LOADABLE PLD, 8.5 ns, PBGA676
封裝： 27 X 27 MM, 1.60 MM HEIGHT, 1 MM PITCH, FBGA-676
文件頁數(shù)： 14/57頁
文件大?。?/td> 1166K
代理商： CY39200V676-167MBC
PRELIMINARY
Delta39K ISR
CPLD Family
Document #: 38-03039 Rev. **
Page 21 of 57
Cluster Memory Timing Parameter Descriptions Over the Operating Range
Parameter
Description
Asynchronous Mode Parameters
tCLMAA
Cluster memory access time. Delay from address change to read data out
tCLMPWE
Write Enable pulse width
tCLMSA
Address set-up to the beginning of Write Enable with both signals from the same I/O block
tCLMHA
Address hold after the end of Write Enable with both signals from the same I/O block
tCLMSD
Data set-up to the end of Write Enable
tCLMHD
Data hold after the end of Write Enable
Synchronous Mode Parameters
tCLMCYC1
Clock cycle time for flow through read and write operations (from macrocell register through cluster memory
back to a macrocell register in the same cluster)
tCLMCYC2
Clock cycle time for pipelined read and write operations (from cluster memory input register through the
memory to cluster memory output register)
tCLMS
Address, data, and WE set-up time of pin inputs, relative to a global clock
tCLMH
Address, data, and WE hold time of pin inputs, relative to a global clock
tCLMDV1
Global clock to data valid on output pins for flow through data
tCLMDV2
Global clock to data valid on output pins for pipelined data
tCLMMACS1
Cluster memory input clock to macrocell clock in the same cluster
tCLMMACS2
Cluster memory output clock to macrocell clock in the same cluster
tMACCLMS1
Macrocell clock to cluster memory input clock in the same cluster
tMACCLMS2
Macrocell clock to cluster memory output clock in the same cluster
Internal Parameters
tCLMCLAA
Asynchronous cluster memory access time from input of cluster memory to output of cluster memory
相關(guān)PDF資料
PDF描述
CY39200Z208-167NC LOADABLE PLD, 8.5 ns, PQFP208
CY39200Z388-167MGC LOADABLE PLD, 8.5 ns, PBGA388
CY39200Z484-167BBC LOADABLE PLD, 8.5 ns, PBGA484
CY39200Z676-167MBC LOADABLE PLD, 8.5 ns, PBGA676
CY39100V388B-125MGXC LOADABLE PLD, 10 ns, PBGA388
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY39200V676-181MBC 制造商:Cypress Semiconductor 功能描述:
CY39200V676-181MBXC 功能描述:CPLD - 復(fù)雜可編程邏輯器件 Delta39K 200K 181MHz COM RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
CY39200V676-83MBXC 功能描述:CPLD - 復(fù)雜可編程邏輯器件 Delta39K 200K 83MHz COM RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
CY39200Z208-125BBC 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
CY39200Z208-125BBI 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
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