參數(shù)資料
型號： CY39200V676-167MBC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： PLD
英文描述： LOADABLE PLD, 8.5 ns, PBGA676
封裝： 27 X 27 MM, 1.60 MM HEIGHT, 1 MM PITCH, FBGA-676
文件頁數(shù)： 57/57頁
文件大小： 1166K
代理商： CY39200V676-167MBC
PRELIMINARY
Delta39K ISR
CPLD Family
Document #: 38-03039 Rev. **
Page 9 of 57
Channel Memory Initialization
The channel memory powers up in an undefined state, but is
set to a user-defined known state during configuration. To fa-
cilitate the use of look-up-table (LUT) logic and ROM applica-
tions, the channel memory blocks can be initialized with a giv-
en set of data when the device is configured at power up. For
LUT and ROM applications, the user cannot write to memory
blocks.
Channel Memory Routing Interface
Similar to LBC outputs, the channel memory blocks feature
dedicated tracks in the horizontal and vertical routing channels
for the data outputs and the flag outputs, as shown in
Figure 6. This allows the channel memory blocks to be ex-
panded easily. These dedicated lines can be routed to I/O pins
as chip outputs or to other logic block clusters to be used in
logic equations.
I/O Banks
The Delta39K interfaces the horizontal and vertical routing
channels to the pins through I/O banks. There are 8 I/O banks
per device as shown in Figure 7, and all I/Os from an I/O bank
are located in the same section of a package for PCB layout
convenience.
For each package type, Delta39K devices of different densities
keep given pins in the same I/O banks. This supports and sim-
plifies design migration across densities.
Each I/O bank contains several I/O cells, and each I/O cell
contains an input/output register, an output enable register,
programmable slew rate control and programmable bus hold
control logic. Each I/O cell drives a pin output of the device;
the cell also supplies an input to the device that connects to a
dedicated track in the associated routing channel.
There are four dedicated inputs (GCTl[3:0]) that are used as
Global Control Signals available to every I/O cell. These global
control signals may be used as output enables, register resets
and register clock enables as shown in Figure 8.
Each I/O bank can use any supported I/O standard by supply-
ing appropriate VREF and VCCIO voltages. All the VREF and
VCCIO pins in an I/O bank must be connected to the same VREF
and VCCIO voltage respectively. This requirement restricts the
number of I/O standards supported by an I/O bank at any given
time.
The number of I/Os which can be used in each I/O bank de-
pend on the type of I/O standards and the number of VCCIO
and GND pins being used. This restriction is derived from the
electromigration limit of the VCCIO and GND bussing on the
chip. Please refer to the note on page 17 and the application
note titled “Delta39K Family Device I/O Standards and Config-
urations” for details.
Figure 7. Delta39K I/O Bank Block Diagram
I/O Standards
I/O
Standard
VREF (V)
VCCIO
Termination
Voltage (VTT)
Min.
Max.
LVTTL
N/A
3.3V
N/A
LVCMOS
3.3V
N/A
LVCMOS3
3.0V
N/A
LVCMOS2
2.5V
N/A
LVCMOS18
1.8V
N/A
3.3V PCI
3.3V
N/A
GTL+
0.9
1.1
N/A
1.5
SSTL3 I
1.3
1.7
3.3V
1.5
SSTL3 II
1.3
1.7
3.3V
1.5
SSTL2 I
1.15
1.35
2.5V
1.25
SSTL2 II
1.15
1.35
2.5V
1.25
HSTL I
0.68
0.9
1.5V
0.75
HSTL II
0.68
0.9
1.5V
0.75
HSTL III
0.68
0.9
1.5V
1.5
HSTL IV
0.68
0.9
1.5V
1.5
Delta39K
bank
0
bank
1
bank
4
bank
5
bank 2
bank 3
bank 6
bank 7
Delta39K
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PDF描述
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY39200V676-181MBC 制造商:Cypress Semiconductor 功能描述:
CY39200V676-181MBXC 功能描述:CPLD - 復(fù)雜可編程邏輯器件 Delta39K 200K 181MHz COM RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
CY39200V676-83MBXC 功能描述:CPLD - 復(fù)雜可編程邏輯器件 Delta39K 200K 83MHz COM RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
CY39200Z208-125BBC 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
CY39200Z208-125BBI 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
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