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參數(shù)資料
| 型號： | CY505YC64DTT |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 18/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLK CK505 BROADWATER 64TSSOP |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 類型： | 時(shí)鐘/頻率發(fā)生器 |
| PLL： | 是 |
| 主要目的： | Intel CPU 服務(wù)器 |
| 輸入： | 晶體 |
| 輸出： | HCSL，LVCMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:24 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 400.9MHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-TFSOP （0.240"，6.10mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 64-TSSOP |
| 包裝： | 帶卷 (TR) |
CY505YC64D
......................Document #: 001-03543 Rev *E Page 3 of 24
41, 40
SRCT/C[6]
O, DIF 100 MHz Differential serial reference clocks.
42
VSS_SRC
GND
Ground for outputs.
44, 43
SRCT7/OE#_8
SRCC7/OE#_6
I/O,
Dif
100 MHz Differential serial reference clocks/3.3V OE#8 Input controlling
SRC8/3.3V OE#6 Input controlling SRC6. Default SRC7.
45
VDD_SRC_IO
PWR
0.7V power supply for SRC outputs.
47, 46
SRCT8/CPUT2_ITPT,
SRCC8/CPUC2_ITPC
O, DIF Selectable differential CPU or SRC clock output. ITP_EN = 0 @ CK_PWRGD
assertion = SRC8
ITP_EN = 1 @ CK_PWRGD assertion = CPU2
48
IO_VOUT
O
Integrated Linear Regulator Control.
49
VDD_CPU_IO
PWR
0.7V Power supply for CPU outputs.
51, 50
CPUT/C[1]
O, DIF Differential CPU clock outputs. Note: CPU1 is the iAMT clock and is on in that
mode.
52
VSS_CPU
GND
Ground for outputs.
54, 53
CPUT/C[0]
O, DIF Differential CPU clock outputs. Note: CPU1 is the iAMT clock and is on in that
mode.
55
VDD_CPU
PWR
3.3V Power supply for CPU PLL.
56
CK_PWRGD/PWRDWN#
I
3.3V LVTTL input. This pin is a level sensitive strobe used to latch the FS_A,
FS_B, FS_C, FS_D, SRC5_SEL, and ITP_EN.
After CK_PWRGD (active HIGH) assertion, this pin becomes a real-time input
for asserting power down (active LOW).
57
FSB/TEST_MODE
I
3.3V tolerant input for CPU frequency selection.
Selects Ref/N or Tri-state when in test mode
0 = Tri-state, 1 = Ref/N.
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifica-
tions.
58
VSS_REF
GND
Ground for outputs.
59
XOUT
O, SE 14.318 MHz Crystal output.
60
XIN
I
14.318 MHz Crystal input.
61
VDD_REF
PWR
3.3V Power supply for outputs and also maintains SMBUS registers during
power-down.
62
REF0/FSC/TEST_SEL
I/O
3.3V tolerant input for CPU frequency selection/fixed 14.318 clock output.
Selects test mode if pulled to VIHFS_C when CK_PWRGD is asserted HIGH.
Refer to DC Electrical Specifications table for VILFS_C, VIMFS_C, VIHFS_C speci-
fications.
63
SMB_DATA
I/O
SMBus compatible SDATA.
64
SMB_CLK
I
SMBus compatible SCLOCK.
Pin Definitions (continued)
Pin No.
Name
Type
Description
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