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參數(shù)資料
| 型號： | CY505YC64DTT |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 19/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLK CK505 BROADWATER 64TSSOP |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 類型： | 時(shí)鐘/頻率發(fā)生器 |
| PLL： | 是 |
| 主要目的： | Intel CPU 服務(wù)器 |
| 輸入： | 晶體 |
| 輸出： | HCSL，LVCMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:24 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 400.9MHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-TFSOP （0.240"，6.10mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 64-TSSOP |
| 包裝： | 帶卷 (TR) |
CY505YC64D
......................Document #: 001-03543 Rev *E Page 4 of 24
Frequency Select Pin (FSA, FSB, FSC, and FSD)
To achieve host clock frequency selection, apply the appro-
priate logic levels to FS_A, FS_B, FS_C, and FS_D inputs
before VTT_PWRGD# assertion (as seen by the clock synthe-
sizer). When VTT_PWRGD# is sampled LOW by the clock
chip (indicating processor VTT voltage is stable), the clock
chip samples the FS_A, FS_B, FS_C, and FS_D input values.
For all logic levels of FS_A, FS_B, FS_C, FS_D, and FS_E,
VTT_PWRGD# employs a one-shot functionality, in that once
a valid LOW on VTT_PWRGD# has been sampled, all further
VTT_PWRGD#, FS_A, FS_B, FS_C, and FS_D transitions will
be ignored, except in test mode.
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers, can be individually enabled or disabled.
The registers associated with the Serial Data Interface
initialize to their default setting upon power-up, and therefore
use of this interface is optional. Clock device register changes
are normally made upon system initialization, if any are
required. The interface cannot be used during system
operation for power management functions.
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, the bytes must be accessed in
sequential order from lowest to highest byte (most significant
bit first) with the ability to stop after any complete byte has
been transferred. For byte write and byte read operations, the
system controller can access individually indexed bytes. The
offset of the indexed byte is encoded in the command code,
as described in Table 2.
The block write and block read protocol is outlined in Table 3
while Table 4 outlines the corresponding byte write and byte
read protocol. The slave receiver address is 11010010 (D2h)
.
Frequency Select Pin (FSA, FSB, FSC, and FSD)
Input Conditions
Output Frequency
FSD
FSC
FSB
FSA
CPU
(MHz)
SRC
(MHz)
SATA
(MHz)
DOT96
(MHz)
USB
(MHz)
PCI
(MHz)
REF
(MHz)
FSEL_3
FSEL_2
FSEL_1
FSEL_0
0101
100
96
48
33.3
14.318
0001
133
100
96
48
33.3
14.318
0011
166
100
96
48
33.3
14.318
0010
200
100
96
48
33.3
14.318
0000
266
100
96
48
33.3
14.318
0100
333
100
96
48
33.3
14.318
0110
400
100
96
48
33.3
14.318
0111
200
100
96
48
33.4
14.318
1101
100.9
100
96
48
33.3
14.318
1001
133.9
100
96
48
33.3
14.318
1011
166.9
100
96
48
33.3
14.318
1010
200.9
100
96
48
33.3
14.318
1000
266.9
100
96
48
33.3
14.318
1100
333.9
100
96
48
33.3
14.318
1110
400.9
100
96
48
33.3
14.318
1111
200.9
100
96
48
33.3
14.318
Table 2. Command Code Definition
Bit
Description
7
0 = Block read or block write operation, 1 = Byte read or byte write operation
(6:0)
Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be
'0000000'
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