- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄9618 > CY505YC64DTT (Silicon Laboratories Inc)IC CLK CK505 BROADWATER 64TSSOP PDF資料下載
參數(shù)資料
| 型號： | CY505YC64DTT |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 2/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLK CK505 BROADWATER 64TSSOP |
| 標準包裝： | 2,000 |
| 類型： | 時鐘/頻率發(fā)生器 |
| PLL： | 是 |
| 主要目的： | Intel CPU 服務器 |
| 輸入： | 晶體 |
| 輸出： | HCSL，LVCMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:24 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 400.9MHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-TFSOP （0.240"，6.10mm 寬） |
| 供應商設備封裝： | 64-TSSOP |
| 包裝： | 帶卷 (TR) |
CY505YC64D
....................Document #: 001-03543 Rev *E Page 10 of 24
1
0
BC1
Byte count
0
1
BC0
Byte count
Byte 12 Byte Count (continued)
Bit
@Pup
Name
Description
Byte 13 Control Register 13
Bit
@Pup
Name
Description
7
1
USB drive strength
USB drive strength, 0 = Low, 1= High
6
1
PCI/PCIF drive strength
PCI drive strength, 0 = Low, 1 = High
5
0
PLL1_Spread
Select percentage of spread for PLL1, 0 = 0.5%, 1=1%
4
1
SATA_SS_EN
Enable SATA spread modulation,
0 = Spread Disabled 1 = Spread Enabled
3
1
CPU[T/C]2
Allow control of CPU2 with assertion of CPU_STOP#
0 = Free running, 1 = Stopped with CPU_STOP#
2
1
CPU[T/C]1
Allow control of CPU1 with assertion of CPU_STOP#
0 = Free running, 1 = Stopped with CPU_STOP#
1
CPU[T/C]0
Allow control of CPU0 with assertion of CPU_STOP#
0 = Free running, 1 = Stopped with CPU_STOP#
0
1
SW_PCI
SW PCI_STP# Function
0 = SW PCI_STP assert, 1 = SW PCI_STP deassert
When this bit is set to 0, all STOPPABLE PCI, PCIF and SRC outputs will
be stopped in a synchronous manner with no short pulses.
When this bit is set to 1, all STOPPED PCI, PCIF and SRC outputs will
resume in a synchronous manner with no short pulses.
Byte 14 Control Register 14
Bit
@Pup
Name
Description
7
0
CPU_DAF_N7
If Prog_CPU_EN is set, the values programmed in CPU_DAF_N[8:0] and
CPU_DAF_M[6:0] will be used to determine the CPU output frequency. The
setting of the FS_Override bit determines the frequency ratio for CPU and
other output clocks. When it is cleared, the same frequency ratio stated in
the Latched FS[D:A] register will be used. When it is set, the frequency ratio
stated in the FSEL[3:0] register will be used
6
0
CPU_DAF_N6
5
0
CPU_DAF_N5
4
0
CPU_DAF_N4
3
0
CPU_DAF_N3
2
0
CPU_DAF_N2
1
0
CPU_DAF_N1
0
CPU_DAF_N0
Byte 15 Control Register 15
Bit
@Pup
Name
Description
7
0
CPU_DAF_N8
See Byte 14 for description
6
0
CPU_DAF_M6
If Prog_CPU_EN is set, the values programmed are in CPU_FSEL_N[8:0]
and CPU_FSEL_M[6:0] will be used to determine the CPU output
frequency. The setting of the FS_Override bit determines the frequency
ratio for CPU and other output clocks. When it is cleared, the same
frequency ratio stated in the Latched FS[D:A] register will be used. When it
is set, the frequency ratio stated in the FSEL[3:0] register will be used
5
0
CPU_DAF_M5
4
0
CPU_DAF_M4
3
0
CPU_DAF_M3
2
0
CPU_DAF_M2
1
0
CPU_DAF_M1
0
CPU_DAF_M0
相關PDF資料 |
PDF描述 |
|---|---|
| VI-BTM-MW-F1 | CONVERTER MOD DC/DC 10V 100W |
| CS3106A-36-79S | CONN PLUG 20POS STRAIGHT W/SCKT |
| D38999/24FJ24PA | CONN RCPT 24POS JAM NUT W/PINS |
| VI-BTL-MW-F2 | CONVERTER MOD DC/DC 28V 100W |
| MS27467T17B35J | CONN PLUG 55POS STRAIGHT W/SCKT |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CY50C475Z | 制造商:PHILIPS 功能描述:Miniature Monolithic Epoxy Coated Ceramic Radial Leads Capacitor - 4.7uF 50dcV +80-20% |
| CY512 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Stepper System Controller |
| CY512P | 制造商:CYLINK 功能描述:512P |
| CY525 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Stepper System Controller |
| CY525A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Stepper Motor Controller/Driver |
發(fā)布緊急采購，3分鐘左右您將得到回復。