- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄170346 > CY62126DV30LL-70ZIT (CYPRESS SEMICONDUCTOR CORP) 64K X 16 STANDARD SRAM, 70 ns, PDSO44 PDF資料下載
參數(shù)資料
| 型號： | CY62126DV30LL-70ZIT |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | SRAM |
| 英文描述： | 64K X 16 STANDARD SRAM, 70 ns, PDSO44 |
| 封裝： | TSOP2-44 |
| 文件頁數(shù)： | 11/13頁 |
| 文件大?。?/td> | 250K |
| 代理商： | CY62126DV30LL-70ZIT |
CY62126DV30
MoBL
Document #: 38-05230 Rev. *G
Page 7 of 13
Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled)[15, 16]
Read Cycle No. 2 (OE Controlled)[16, 17]
Notes:
15. Device is continuously selected. OE, CE = VIL, BHE, BLE = VIL.
16. WE is HIGH for Read cycle.
17. Address valid prior to or coincident with CE, BHE, BLE transition LOW.
ADDRESS
DATA OUT
PREVIOUS DATA VALID
DATA VALID
tRC
tAA
tOHA
50%
DATA VALID
tRC
tACE
tLZBE
tLZCE
tPU
DATA OUT
HIGH IMPEDANCE
IMPEDANCE
ICC
ISB
tHZOE
tHZCE
tPD
OE
CE
HIGH
VCC
SUPPLY
CURRENT
tHZBE
BHE/BLE
tLZOE
ADDRESS
tDOE
tLZOE
tDBE
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY62148L-100SC | 512K X 8 STANDARD SRAM, 100 ns, PDSO32 |
| CY74FCT158ATPC | FCT SERIES, QUAD 2 LINE TO 1 LINE MULTIPLEXER, INVERTED OUTPUT, PDIP16 |
| CY74FCT377ATQC | FCT SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO20 |
| CY7B155-12LC | 16K X 16 STANDARD SRAM, 12 ns, CQCC52 |
| CY7B155-15JC | 16K X 16 STANDARD SRAM, 15 ns, PQCC52 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY62126DV30LL-70ZSI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:1-Mbit (64K x 16) Static RAM |
| CY62126DV30LL-70ZSXI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:1-Mbit (64K x 16) Static RAM |
| CY62126DV30LL-70ZXI | 制造商:Rochester Electronics LLC 功能描述: 制造商:Cypress Semiconductor 功能描述: |
| CY62126ESL | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:1-Mbit (64K x 16) Static RAM |
| CY62126ESL_13 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:1-Mbit (64 K x 16) Static RAM |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。