參數(shù)資料
型號(hào)： CY7C057V-12AXC
廠(chǎng)商： CYPRESS SEMICONDUCTOR CORP
元件分類(lèi)： SRAM
英文描述： 3.3V 16K/32K x 36 FLEx36™ Asynchronous Dual-Port Static
中文描述： 32K X 36 DUAL-PORT SRAM, 12 ns, PQFP144
封裝： 20 X 20 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, PLASTIC, TQFP-144
文件頁(yè)數(shù)： 14/26頁(yè)
文件大?。?/td> 713K
代理商： CY7C057V-12AXC
CY7C056V
CY7C057V
Document #: 38-06055 Rev. *E
Page 21 of 26
pin and to the bus size select (SIZE) pin will select long-word
(36-bit) operation. A logic “1” level applied to the bus match
select (BM) pin will enable either byte or word bus width
operation on the right port I/Os depending on the logic level
applied to the SIZE pin. The level of bus match select (BM) must
be static throughout device operation.
Normally, the bus size select (SIZE) pin would have no
standard-cycle application when BM = LOW and the device is in
long-word (36-bit) operation. A “special” mode has been added
however to disable ALL right port I/Os while the chip is active.
This I/O disable mode is implemented when SIZE is forced to a
logic “1” while BM is at a logic “0”. It allows the bus-matched port
to support a chip enable “Don’t care” semaphore read/write
access similar to that provided on the left port of the device when
all Byte Select (B0–3) control inputs are deselected.
The bus size select (SIZE) pin selects either a byte or word data
arrangement on the right port when the bus match select (BM)
pin is HIGH. A logic “1” on the SIZE pin when the BM pin is HIGH
selects a byte bus (9-bit) data arrangement). A logic “0” on the
SIZE pin when the BM pin is HIGH selects a word bus (18-bit)
data arrangement. The level of the bus size select (SIZE) must
also be static throughout normal device operation.
Long-Word (36-bit) Operation
Bus match select (BM) and bus size select (SIZE) set to a logic
“0” will enable standard cycle long-word (36-bit) operation. In this
mode, the right port’s I/O operates essentially in an identical
fashion as does the left port of the dual-port SRAM. However no
byte select control is available. All 36 bits of the long-word are
shifted into and out of the right port’s I/O buffer stages. All read
and write timing parameters may be identical with respect to the
two data ports. When the right port is configured for a long-word
size, word address (WA), and byte Address (BA) pins have no
application and their inputs are “Don’t Care”[55] for the external
user.
Word (18-bit) Operation
Word (18-bit) bus sizing operation is enabled when bus match
select (BM) is set to a logic “1” and the bus sze select (SIZE) pin
is set to a logic “0.” In this mode, 18 bits of data are ported
through I/O0R–17R. The level applied to the word address (WA)
pin during word bus size operation determines whether the
most-significant or least-significant data bits are ported through
the I/O0R–17R pins in an Upper word/Lower word select fashion
(note that when the right port is configured for word size
operation, the Byte Address pin has no application and its input
is “Don’t care”[55]).
Device operation is accomplished by treating the WA pin as an
additional address input and using standard cycle address and
data setup/hold times. When transferring data in word (18-bit)
bus match format, the unused I/O18R–35R pins are three-stated.
Byte (9-bit) Operation
Byte (9-bit) bus sizing operation is enabled when bus match
select (BM) is set to a logic “1” and the bus size select (SIZE) pin
is set to a logic “1.” In this mode, data is ported through I/O0R–8R
in four groups of 9-bit bytes. A particular 9-bit byte group is
selected according to the levels applied to the word address
(WA) and byte address (BA) input pins.
Device operation is accomplished by treating the word address
(WA) pin and the byte address (BA) pins as additional address
inputs having standard cycle address and data set-up/hold
times. When transferring data in byte (9-bit) bus match format,
the unused I/O9R–35R pins are three-stated.
Note
55. Even though a logic level applied to a “Don’t Care” input will not change the logical operation of the dual-port, inputs that are temporarily a “Don’t Care” (along with
unused inputs) must not be allowed to float. They must be forced either HIGH or LOW.
I/Os
Rank
WA
BA
I/O27R–35R
Upper-MSB
1
I/O18R–26R
Lower-MSB
1
0
I/O9R–17R
Upper-MSB
0
1
I/O0R–8R
Lower-MSB
0
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參數(shù)描述
CY7C057V-12AXCT 功能描述:IC SRAM 1.152MBIT 12NS 144LQFP RoHS:是 類(lèi)別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類(lèi)型:移動(dòng) SDRAM 存儲(chǔ)容量:256M（8Mx32） 速度:133MHz 接口:并聯(lián) 電源電壓:1.7 V ~ 1.95 V 工作溫度:-40°C ~ 85°C 封裝/外殼:90-VFBGA 供應(yīng)商設(shè)備封裝:90-VFBGA（8x13） 包裝:帶卷 (TR) 其它名稱(chēng):557-1327-2
CY7C057V-12BBC 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 3.3V 16Kx36 Aync COM FLEx36 DualPort 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪(fǎng)問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
CY7C057V-15AC 功能描述:IC SRAM 1.152MBIT 15NS 144LQFP RoHS:否 類(lèi)別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:96 系列:- 格式 - 存儲(chǔ)器:閃存 存儲(chǔ)器類(lèi)型:FLASH 存儲(chǔ)容量:16M（2M x 8，1M x 16） 速度:70ns 接口:并聯(lián) 電源電壓:2.65 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-TFSOP（0.724"，18.40mm 寬） 供應(yīng)商設(shè)備封裝:48-TSOP 包裝:托盤(pán)
CY7C057V-15AI 制造商:Cypress Semiconductor 功能描述:SRAM Chip Async Dual 3.3V 1.125M-Bit 32K x 36 15ns 144-Pin TQFP
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