參數(shù)資料
型號(hào)： CY7C0832V-167AXC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類(lèi)： SRAM
英文描述： 256K X 18 DUAL-PORT SRAM, 4 ns, PQFP120
封裝： 14 X 14 MM, 1.40 MM HEIGHT, LEAD FREE, TQFP-120
文件頁(yè)數(shù)： 1/32頁(yè)
文件大?。?/td> 895K
代理商： CY7C0832V-167AXC
3.3V 64K/128K x 36 and 128K/256K x 18
Synchronous Dual-Port RAM
CY7C0851V/CY7C0852V
CY7C0831V/CY7C0832V
Cypress Semiconductor Corporation
3901 North First Street
San Jose
, CA 95134
408-943-2600
Document #: 38-06059 Rev. *I
Revised June 03, 2004
Features
True dual-ported memory cells that allow simultaneous
access of the same memory location
Synchronous pipelined operation
Organization of 2M and 4.5M devices
— 128K × 36 (CY7C0852V)
— 64K × 36 (CY7C0851V)
— 256K × 18 (CY7C0832V)
— 128K × 18 (CY7C0831V)
Pipelined output mode allows fast 167-MHz operation
0.18-micron CMOS for optimum speed and power
High-speed clock to data access: 4.0 ns (max.)
3.3V low operating power
— Active = 225 mA (typical)
— Standby = 55 mA (typical)
Interrupt flags for message passing
Global master reset
Separate byte enables on both ports
Commercial and industrial temperature ranges
IEEE 1149.1-compatible JTAG boundary scan
172-ball BGA (1 mm pitch) (15 mm × 15 mm)
120-pin TQFP (14 mm × 14 mm × 1.4 mm)
176-pin TQFP (24 mm × 24 mm × 1.4 mm)
FLEx36
devices are footprint upgradeable from 2M to
4M to 9M
Counter wrap around control
— Internal mask register controls counter wrap-around
— Counter-interrupt flags to indicate wrap-around
— Memory block retransmit operation
Counter readback on address lines
Mask register readback on address lines
Dual Chip Enables on both ports for easy depth
expansion
Functional Description
The CY7C0851V/CY7C0852V/CY7C0831VCY7C0832V are
2M and 4.5M pipelined, synchronous, true dual-port static
RAMs that are high-speed, low-power 3.3V CMOS. Two ports
are provided, permitting independent, simultaneous access for
Reads from any location in memory. The result of writing to the
same location by more than one port at the same time is
undefined. Registers on control, address, and data lines allow
for minimal set-up and hold time.
During a Read operation, data is registered for decreased
cycle time. Clock to data valid tCD2 = 4.0 ns at 167 MHz. Each
port contains a burst counter on the input address register.
After externally loading the counter with the initial address, the
counter will increment the address internally (more details to
follow). The internal Write pulse width is independent of the
duration of the R/W input signal. The internal Write pulse is
self-timed to allow the shortest possible cycle times.
A HIGH on CE0 or LOW on CE1 for one clock cycle will power
down the internal circuitry to reduce the static power
consumption. One cycle with chip enables asserted is required
to reactivate the outputs.
Counter enable (CNTEN) inputs are provided to stall the
operation of the address input and utilize the internal address
generated by the internal counter for fast, interleaved memory
applications. A port’s burst counter is loaded when the port’s
address strobe (ADS) and CNTEN signals are LOW. When the
port’s CNTEN is asserted and the ADS is deasserted, the
address counter will increment on each LOW to HIGH
transition of that port’s clock signal. This will Read/Write one
word from/into each successive address location until CNTEN
is deasserted. The counter can address the entire memory
array, and will loop back to the start. Counter reset (CNTRST)
is used to reset the unmasked portion of the burst counter to
0s. A counter-mask register is used to control the counter
wrap. The counter and mask register operations are described
in more detail in the following sections.
New features added to the CY7C0851V/CY7C0852V/
CY7C0831V/CY7C0832V devices include: readback of
burst-counter internal address value on address lines,
counter-mask registers to control the counter wrap-around,
counter interrupt (CNTINT) flags, readback of mask register
value on address lines, retransmit functionality, interrupt flags
for message passing, JTAG for boundary scan, and
asynchronous Master Reset (MRST).
Cypress offers an upgrade to a 9M synchronous Dual Port with
a compatible footprint. Please see the application note
Upgrading the 4-Meg (CY7C0852) Dual-Port to a 9-Meg
(CY7C0853) Dual-Port for more details.
CY7C093794V CY7C093894V CY7C09289V CY7C09369V CY7C09379V CY7C09389V3.3V 64K/128K x 36 and 128K/256K x 18
Synchronous Dual-Port RAM
相關(guān)PDF資料
PDF描述
CY7C0851AV-133AXC FLEx36™ 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM
CY7C0851AV-133BBC FLEx36™ 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM
CY7C0851AV-167AXC FLEx36™ 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM
CY7C0851AV-167BBC FLEx36™ 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM
CY7C0852AV-133BBC FLEx36™ 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY7C0832V-167BBC 制造商:Cypress Semiconductor 功能描述:SRAM SYNC DUAL 3.3V 4.5MBIT 256KX18 4NS 144FBGA - Bulk
CY7C0833AV-100BBC 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Dual 3.3V 9M-Bit 512K x 18 144-Pin FBGA
CY7C0833AV-133BBC 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Dual 3.3V 9M-Bit 512K x 18 4.7ns 144-Pin FBGA 制造商:Rochester Electronics LLC 功能描述:
CY7C0833AV-133BBI 制造商:Cypress Semiconductor 功能描述:
CY7C0833V-100BBC 制造商:Cypress Semiconductor 功能描述:SRAM SYNC DUAL 3.3V 9MBIT 512KX18 5NS 144FBGA - Bulk
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